i40e: PFINT_ITR0 register

i40e_bm/i40e_bm.cc

@@ -245,6 +245,16 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
                 val = regs.pfint_dyn_ctl0;
                 break;
 
+            case I40E_PFINT_ITR0(0):
+                val = regs.pfint_itr0[0];
+                break;
+            case I40E_PFINT_ITR0(1):
+                val = regs.pfint_itr0[1];
+                break;
+            case I40E_PFINT_ITR0(2):
+                val = regs.pfint_itr0[2];
+                break;
+
             case I40E_GLPCI_CNF2:
                 val = ((NUM_PFINTS - 2) << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) |
                     (2 << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT); /* that is ugly,
@@ -488,6 +498,15 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
             case I40E_PFINT_DYN_CTL0:
                 regs.pfint_dyn_ctl0 = val;
                 break;
+            case I40E_PFINT_ITR0(0):
+                regs.pfint_itr0[0] = val;
+                break;
+            case I40E_PFINT_ITR0(1):
+                regs.pfint_itr0[1] = val;
+                break;
+            case I40E_PFINT_ITR0(2):
+                regs.pfint_itr0[2] = val;
+                break;
 
             case I40E_PFHMC_SDCMD:
                 regs.pfhmc_sdcmd = val;

i40e_bm/i40e_bm.h

@@ -443,6 +443,7 @@ protected:
     static const uint32_t NUM_PFINTS = 512;
     static const uint32_t NUM_VSIS = 384;
     static const uint16_t MAX_MTU = 2048;
+    static const uint8_t NUM_ITR = 3;
 
     struct i40e_regs {
         uint32_t glgen_rstctl;
@@ -451,6 +452,7 @@ protected:
         uint32_t pfint_lnklst0;
         uint32_t pfint_icr0_ena;
         uint32_t pfint_icr0;
+        uint32_t pfint_itr0[NUM_ITR];
 
         uint32_t pfint_dyn_ctl0;
         uint32_t pfint_dyn_ctln[NUM_PFINTS - 1];