i40e: basic transmit seems to work

i40e_bm/i40e_bm.cc

@@ -45,6 +45,7 @@ void i40e_bm::dma_complete(nicbm::DMAOp &op)
 
 void i40e_bm::eth_rx(uint8_t port, const void *data, size_t len)
 {
+    std::cerr << "i40e: received packet len=" << len << std::endl;
 }
 
 void i40e_bm::reg_read(uint8_t bar, uint64_t addr, void *dest, size_t len)

i40e_bm/i40e_bm.h

@@ -86,6 +86,9 @@ class queue_base {
         // called when data is fetched
         virtual void data_fetched(void *desc, uint32_t idx, void *data) = 0;
         virtual void desc_written_back(uint32_t idx);
+        void desc_done(uint32_t idx);
+        // dummy function, needs to be overriden if interrupts are required
+        virtual void interrupt();
 
     public:
         queue_base(uint32_t &reg_head_, uint32_t &reg_tail_);
@@ -166,14 +169,10 @@ class lan_queue_base : public queue_base {
 
         lan &lanmgr;
 
-        // called by base class when a descriptor has been fetched
-        virtual void desc_fetched(void *desc, uint32_t idx);
-        // called by basee class when data for a descriptor has been fetched
-        virtual void data_fetched(void *desc, uint32_t idx, void *data);
-
         void ctx_fetched();
         void ctx_written_back();
 
+        virtual void interrupt();
         virtual void initialize() = 0;
 
     public:
@@ -181,26 +180,45 @@ class lan_queue_base : public queue_base {
         size_t idx;
         uint32_t &reg_ena;
         uint32_t &fpm_basereg;
+        uint32_t &reg_intqctl;
         size_t ctx_size;
         void *ctx;
 
         uint32_t reg_dummy_head;
 
         lan_queue_base(lan &lanmgr_, uint32_t &reg_tail, size_t idx_,
-                uint32_t &reg_ena_, uint32_t &fpm_basereg, uint16_t ctx_size);
+                uint32_t &reg_ena_, uint32_t &fpm_basereg, uint32_t &reg_intqctl,
+                uint16_t ctx_size);
         void enable();
         void disable();
 };
 
 class lan_queue_tx : public lan_queue_base {
     protected:
+        class dma_hwb : public dma_base {
+            protected:
+                lan_queue_tx &queue;
+            public:
+                uint32_t head;
+                uint32_t next_head;
+                dma_hwb(lan_queue_tx &queue_, uint32_t head_, uint32_t qlen);
+                virtual ~dma_hwb();
+                virtual void done();
+        };
+
         bool hwb;
         uint64_t hwb_addr;
 
         virtual void initialize();
+
+        virtual void desc_fetched(void *desc, uint32_t idx);
+        virtual void data_fetched(void *desc, uint32_t idx, void *data);
+        void desc_writeback(const void *desc, uint32_t idx);
+
     public:
         lan_queue_tx(lan &lanmgr_, uint32_t &reg_tail, size_t idx,
-                uint32_t &reg_ena, uint32_t &fpm_basereg);
+                uint32_t &reg_ena, uint32_t &fpm_basereg,
+                uint32_t &reg_intqctl);
 };
 
 class lan_queue_rx : public lan_queue_base {
@@ -211,9 +229,14 @@ class lan_queue_rx : public lan_queue_base {
         bool crc_strip;
 
         virtual void initialize();
+
+        virtual void desc_fetched(void *desc, uint32_t idx);
+        virtual void data_fetched(void *desc, uint32_t idx, void *data);
+
     public:
         lan_queue_rx(lan &lanmgr_, uint32_t &reg_tail, size_t idx,
-                uint32_t &reg_ena, uint32_t &fpm_basereg);
+                uint32_t &reg_ena, uint32_t &fpm_basereg,
+                uint32_t &reg_intqctl);
 };
 
 // rx tx management
@@ -251,6 +274,8 @@ protected:
     friend class host_mem_cache;
     friend class lan;
     friend class lan_queue_base;
+    friend class lan_queue_rx;
+    friend class lan_queue_tx;
     friend class shadow_ram;
 
     static const unsigned BAR_REGS = 0;

i40e_bm/i40e_lan.cc

@@ -19,9 +19,11 @@ lan::lan(i40e_bm &dev_, size_t num_qs_)
 
     for (size_t i = 0; i < num_qs; i++) {
         rxqs[i] = new lan_queue_rx(*this, dev.regs.qrx_tail[i], i,
-                dev.regs.qrx_ena[i], dev.regs.glhmc_lanrxbase[0]);
+                dev.regs.qrx_ena[i], dev.regs.glhmc_lanrxbase[0],
+                dev.regs.qint_rqctl[i]);
         txqs[i] = new lan_queue_tx(*this, dev.regs.qtx_tail[i], i,
-                dev.regs.qtx_ena[i], dev.regs.glhmc_lantxbase[0]);
+                dev.regs.qtx_ena[i], dev.regs.glhmc_lantxbase[0],
+                dev.regs.qint_tqctl[i]);
     }
 }
 
@@ -51,22 +53,15 @@ void lan::tail_updated(uint16_t idx, bool rx)
 }
 
 lan_queue_base::lan_queue_base(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
-        uint32_t &reg_ena_, uint32_t &fpm_basereg_, uint16_t ctx_size_)
+        uint32_t &reg_ena_, uint32_t &fpm_basereg_, uint32_t &reg_intqctl_,
+        uint16_t ctx_size_)
     : queue_base(reg_dummy_head, reg_tail_), lanmgr(lanmgr_), enabling(false),
     idx(idx_), reg_ena(reg_ena_), fpm_basereg(fpm_basereg_),
-    ctx_size(ctx_size_)
+    reg_intqctl(reg_intqctl_), ctx_size(ctx_size_)
 {
     ctx = new uint8_t[ctx_size_];
 }
 
-void lan_queue_base::desc_fetched(void *desc, uint32_t idx)
-{
-}
-
-void lan_queue_base::data_fetched(void *desc, uint32_t idx, void *data)
-{
-}
-
 void lan_queue_base::enable()
 {
     if (enabling || enabled)
@@ -107,6 +102,34 @@ void lan_queue_base::disable()
     reg_ena &= ~I40E_QRX_ENA_QENA_STAT_MASK;
 }
 
+void lan_queue_base::interrupt()
+{
+    uint32_t qctl = reg_intqctl;
+    std::cerr << "lanq: interrupt intctl=" << qctl << std::endl;
+
+    uint16_t msix_idx = (qctl & I40E_QINT_TQCTL_MSIX_INDX_MASK) >>
+        I40E_QINT_TQCTL_ITR_INDX_SHIFT;
+    uint8_t msix0_idx = (qctl & I40E_QINT_TQCTL_MSIX0_INDX_MASK) >>
+        I40E_QINT_TQCTL_MSIX0_INDX_SHIFT;
+    bool cause_ena = !!(qctl & I40E_QINT_TQCTL_CAUSE_ENA_MASK);
+
+    if (!cause_ena) {
+        std::cerr << "lanq: interrupt cause disabled" << std::endl;
+        return;
+    }
+
+    if (msix_idx != 0) {
+        std::cerr << "TODO: only int 0 is supported" << std::endl;
+        abort();
+    }
+
+    // TODO throttling?
+    std::cerr << "   setting int0.qidx=" << msix0_idx << std::endl;
+    lanmgr.dev.regs.pfint_icr0 |= I40E_PFINT_ICR0_INTEVENT_MASK |
+        (1 << (I40E_PFINT_ICR0_QUEUE_0_SHIFT + msix0_idx));
+    runner->msi_issue(0);
+}
+
 lan_queue_base::qctx_fetch::qctx_fetch(lan_queue_base &lq_)
     : lq(lq_)
 {
@@ -119,8 +142,9 @@ void lan_queue_base::qctx_fetch::done()
 }
 
 lan_queue_rx::lan_queue_rx(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
-        uint32_t &reg_ena_, uint32_t &reg_fpmbase_)
-    : lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_, 32)
+        uint32_t &reg_ena_, uint32_t &reg_fpmbase_, uint32_t &reg_intqctl_)
+    : lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_,
+            reg_intqctl_, 32)
 {
 }
 
@@ -166,9 +190,22 @@ void lan_queue_rx::initialize()
         " crcstrip=" << crc_strip << " rxmax=" << rxmax << std::endl;
 }
 
+void lan_queue_rx::desc_fetched(void *desc_ptr, uint32_t didx)
+{
+    std::cerr << "rxq: desc fetched" << std::endl;
+
+    //union i40e_32byte_rx_desc *desc = desc_ptr;
+}
+
+void lan_queue_rx::data_fetched(void *desc, uint32_t didx, void *data)
+{
+    std::cerr << "rxq: data fetched" << std::endl;
+}
+
 lan_queue_tx::lan_queue_tx(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
-        uint32_t &reg_ena_, uint32_t &reg_fpmbase_)
-    : lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_, 128)
+        uint32_t &reg_ena_, uint32_t &reg_fpmbase_, uint32_t &reg_intqctl)
+    : lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_,
+            reg_intqctl, 128)
 {
     desc_len = 16;
 }
@@ -200,3 +237,79 @@ void lan_queue_tx::initialize()
         " len=" << len << " hwb=" << hwb << " hwb_addr=" << hwb_addr <<
         std::endl;
 }
+
+void lan_queue_tx::desc_fetched(void *desc_buf, uint32_t didx)
+{
+    std::cerr << "txq: desc fetched" << std::endl;
+
+    struct i40e_tx_desc *desc = reinterpret_cast<struct i40e_tx_desc *>(desc_buf);
+    uint64_t d1 = desc->cmd_type_offset_bsz;
+
+    uint8_t dtype = (d1 & I40E_TXD_QW1_DTYPE_MASK) >> I40E_TXD_QW1_DTYPE_SHIFT;
+    if (dtype != I40E_TX_DESC_DTYPE_DATA) {
+        // TODO
+        std::cerr << "txq: only support data descriptors" << std::endl;
+        abort();
+    }
+
+    uint16_t cmd = (d1 & I40E_TXD_QW1_CMD_MASK) >> I40E_TXD_QW1_CMD_SHIFT;
+    if (!(cmd & I40E_TX_DESC_CMD_EOP)) {
+        std::cerr << "txq: TODO multi descriptor packet" << std::endl;
+        abort();
+    }
+    uint16_t len = (d1 & I40E_TXD_QW1_TX_BUF_SZ_MASK) >>
+        I40E_TXD_QW1_TX_BUF_SZ_SHIFT;
+
+    std::cerr << "  bufaddr=" << desc->buffer_addr << " len=" << len << std::endl;
+
+    data_fetch(desc_buf, didx, desc->buffer_addr, len);
+}
+
+void lan_queue_tx::data_fetched(void *desc_buf, uint32_t didx, void *data)
+{
+    std::cerr << "txq: data fetched" << std::endl;
+    struct i40e_tx_desc *desc = reinterpret_cast<struct i40e_tx_desc *>(desc_buf);
+    uint64_t d1 = desc->cmd_type_offset_bsz;
+    uint16_t len = (d1 & I40E_TXD_QW1_TX_BUF_SZ_MASK) >>
+        I40E_TXD_QW1_TX_BUF_SZ_SHIFT;
+
+    runner->eth_send(data, len);
+
+    desc->buffer_addr = 0;
+    desc->cmd_type_offset_bsz = I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT;
+    desc_writeback(desc_buf, didx);
+}
+
+void lan_queue_tx::desc_writeback(const void *desc, uint32_t didx)
+{
+    if (!hwb) {
+        // if head index writeback is disabled we need to write descriptor back
+        lan_queue_base::desc_writeback(desc, idx);
+    } else {
+        // else we just need to write the index back
+        dma_hwb *dma = new dma_hwb(*this, didx, (didx + 1) % len);
+        dma->dma_addr = hwb_addr;
+
+        std::cerr << "hwb=" << *((uint32_t *) dma->data) << std::endl;
+        runner->issue_dma(*dma);
+    }
+}
+
+lan_queue_tx::dma_hwb::dma_hwb(lan_queue_tx &queue_, uint32_t index_, uint32_t next)
+    : queue(queue_), head(index_), next_head(next)
+{
+    data = &next_head;
+    len = 4;
+    write = true;
+}
+
+lan_queue_tx::dma_hwb::~dma_hwb()
+{
+}
+
+void lan_queue_tx::dma_hwb::done()
+{
+    std::cerr << "txq: tx head written back" << std::endl;
+    queue.desc_written_back(head);
+    delete this;
+}

i40e_bm/i40e_queues.cc

@@ -95,13 +95,24 @@ void queue_base::desc_writeback_indirect(const void *desc, uint32_t idx,
     runner->issue_dma(*data_dma);
 }
 
+void queue_base::desc_done(uint32_t idx)
+{
+    reg_head = (idx + 1) % len;
+    trigger_fetch();
+}
+
+void queue_base::interrupt()
+{
+}
+
 void queue_base::desc_written_back(uint32_t idx)
 {
     if (!enabled)
         return;
 
     std::cerr << "descriptor " << idx << " written back" << std::endl;
-    reg_head = (idx + 1) % len;
+    desc_done(idx);
+    interrupt();
 }
 
 queue_base::dma_fetch::dma_fetch(queue_base &queue_, size_t len_)
@@ -161,7 +172,6 @@ queue_base::dma_wb::~dma_wb()
 void queue_base::dma_wb::done()
 {
     queue.desc_written_back(index);
-    queue.trigger_fetch();
     delete this;
 }