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ycai
simbricks
Commits
792075ed
"git@developer.sourcefind.cn:SIYIXNI/vllm.git" did not exist on "96b6f475dda40a0c7d557f73c36fe09c07be2e9c"
Unverified
Commit
792075ed
authored
Sep 19, 2024
by
Jakob Görgen
Browse files
reversed changes reagrding default initialization of component interfaces
parent
74fcfa90
Changes
3
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3 changed files
with
4 additions
and
16 deletions
+4
-16
experiments/pyexps/netperf_sysconf.py
experiments/pyexps/netperf_sysconf.py
+0
-8
experiments/simbricks/orchestration/system/eth.py
experiments/simbricks/orchestration/system/eth.py
+2
-4
experiments/simbricks/orchestration/system/pcie.py
experiments/simbricks/orchestration/system/pcie.py
+2
-4
No files found.
experiments/pyexps/netperf_sysconf.py
View file @
792075ed
...
...
@@ -24,8 +24,6 @@ host0 = system.I40ELinuxHost(sys)
pcie0
=
system
.
PCIeHostInterface
(
host0
)
host0
.
add_if
(
pcie0
)
nic0
=
system
.
IntelI40eNIC
(
sys
)
nic0_pci
=
system
.
PCIeDeviceInterface
(
nic0
)
nic0
.
add_if
(
nic0_pci
)
nic0
.
add_ipv4
(
'10.0.0.1'
)
pcichannel0
=
system
.
PCIeChannel
(
pcie0
,
nic0
.
_pci_if
)
...
...
@@ -34,8 +32,6 @@ host1 = system.I40ELinuxHost(sys)
pcie1
=
system
.
PCIeHostInterface
(
host1
)
host1
.
add_if
(
pcie0
)
nic1
=
system
.
IntelI40eNIC
(
sys
)
nic1_pci
=
system
.
PCIeDeviceInterface
(
nic1
)
nic1
.
add_if
(
nic1_pci
)
nic1
.
add_ipv4
(
'10.0.0.2'
)
pcichannel1
=
system
.
PCIeChannel
(
pcie1
,
nic1
.
_pci_if
)
...
...
@@ -46,10 +42,6 @@ switch.add_if(netif0)
netif1
=
system
.
EthInterface
(
switch
)
switch
.
add_if
(
netif1
)
nic0_eth
=
system
.
EthInterface
(
nic0
)
nic0
.
add_if
(
nic0_eth
)
nic1_eth
=
system
.
EthInterface
(
nic1
)
nic1
.
add_if
(
nic1_eth
)
# create channels and connect the switch to the host nics
ethchannel0
=
system
.
EthChannel
(
switch
.
eth_ifs
[
0
],
nic0
.
_eth_if
)
...
...
experiments/simbricks/orchestration/system/eth.py
View file @
792075ed
...
...
@@ -44,16 +44,14 @@ class EthSimpleNIC(base.Component):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
super
().
__init__
(
s
)
self
.
_ip
:
str
|
None
=
None
self
.
_eth_if
:
EthInterface
|
None
=
None
self
.
_eth_if
:
EthInterface
=
EthInterface
(
self
)
def
add_ipv4
(
self
,
ip
:
str
)
->
None
:
assert
self
.
_ip
is
None
self
.
_ip
=
ip
def
add_if
(
self
,
interface
:
EthInterface
)
->
None
:
utils_base
.
has_expected_type
(
obj
=
interface
,
expected_type
=
EthInterface
)
assert
self
.
_eth_if
is
None
self
.
_eth_if
=
interface
raise
Exception
(
"EthSimpleNIC already has ethernet interface"
)
class
BaseEthNetComponent
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
...
...
experiments/simbricks/orchestration/system/pcie.py
View file @
792075ed
...
...
@@ -56,12 +56,10 @@ class PCIeChannel(base.Channel):
class
PCIeSimpleDevice
(
base
.
Component
):
def
__init__
(
self
,
s
:
base
.
System
):
super
().
__init__
(
s
)
self
.
_pci_if
:
PCIeDeviceInterface
|
None
=
None
self
.
_pci_if
:
PCIeDeviceInterface
=
PCIeDeviceInterface
(
self
)
def
interfaces
(
self
)
->
list
[
base
.
Interface
]:
return
[
self
.
_pci_if
]
def
add_if
(
self
,
interface
:
PCIeDeviceInterface
)
->
None
:
utils_base
.
has_expected_type
(
obj
=
interface
,
expected_type
=
PCIeDeviceInterface
)
assert
self
.
_pci_if
is
None
self
.
_pci_if
=
interface
\ No newline at end of file
raise
Exception
(
"PCIeSimpleDevice already has PCI device interface"
)
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