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ycai
simbricks
Commits
232952d8
Commit
232952d8
authored
Dec 03, 2020
by
Hejing Li
Browse files
add gem5 system clock arg
parent
a9459e43
Changes
1
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-1
experiments/modes/simulators.py
experiments/modes/simulators.py
+2
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experiments/modes/simulators.py
View file @
232952d8
...
@@ -141,6 +141,7 @@ class QemuHost(HostSim):
...
@@ -141,6 +141,7 @@ class QemuHost(HostSim):
class
Gem5Host
(
HostSim
):
class
Gem5Host
(
HostSim
):
cpu_type_cp
=
'X86KvmCPU'
cpu_type_cp
=
'X86KvmCPU'
cpu_type
=
'TimingSimpleCPU'
cpu_type
=
'TimingSimpleCPU'
sys_clock
=
'1GHz'
def
set_config
(
self
,
nc
):
def
set_config
(
self
,
nc
):
...
@@ -164,7 +165,7 @@ class Gem5Host(HostSim):
...
@@ -164,7 +165,7 @@ class Gem5Host(HostSim):
cmd
=
(
f
'
{
env
.
gem5_path
}
--outdir=
{
env
.
gem5_outdir
(
self
)
}
'
cmd
=
(
f
'
{
env
.
gem5_path
}
--outdir=
{
env
.
gem5_outdir
(
self
)
}
'
f
'
{
env
.
gem5_py_path
}
--caches --l2cache --l3cache '
f
'
{
env
.
gem5_py_path
}
--caches --l2cache --l3cache '
'--l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB '
'--l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB '
f
'--cacheline_size=64 --cpu-clock=
{
self
.
cpu_freq
}
'
f
'--cacheline_size=64 --cpu-clock=
{
self
.
cpu_freq
}
--sys-clock=
{
self
.
sys_clock
}
'
f
'--checkpoint-dir=
{
env
.
gem5_cpdir
(
self
)
}
'
f
'--checkpoint-dir=
{
env
.
gem5_cpdir
(
self
)
}
'
f
'--kernel=
{
env
.
gem5_kernel_path
}
'
f
'--kernel=
{
env
.
gem5_kernel_path
}
'
f
'--disk-image=
{
env
.
hd_raw_path
(
self
.
node_config
.
disk_image
)
}
'
f
'--disk-image=
{
env
.
hd_raw_path
(
self
.
node_config
.
disk_image
)
}
'
...
...
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