GitLab

Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com>

Signed-off-by: Yintong Lu <yintong.lu@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: 1195343015 <1195343015@qq.com>
Signed-off-by: Jiayi Yan <66017932+1195343015@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>

Signed-off-by: Didier Durand <durand.didier@gmail.com>
Signed-off-by: Didier Durand <2927957+didier-durand@users.noreply.github.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>

Signed-off-by: dolpm <34420038+dolpm@users.noreply.github.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>

[CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: Boyuan Feng <boyuan@meta.com>
Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

[cpu][perf] Accelerate unquantized-linear for AArch64 through oneDNN/ACL and weight prepack (#25948)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

Signed-off-by: Nikhil Gupta <nikhil.gupta2@arm.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

[Bugfix][Apple Silicon] fix missing symbols when build from source on Mac with Apple Silicon (#21380)
Signed-off-by: Yeju Zhou <yejuzhou@outlook.com>

Signed-off-by: nishith-fujitsu <nishith.jaiswal@fujitsu.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: mgoin <mgoin64@gmail.com>

Signed-off-by: Yong Hoon Shin <yhshin@meta.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>

Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
Co-authored-by: Micah Williamson <micah.williamson@amd.com>

Signed-off-by: Lu Fang <lufang@fb.com>

Co-authored-by: Sage Moore <sage@neuralmagic.com>

[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)