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Replace NULL with nullptr when adding kernel arguments

This ensures that the correct argument size is used when calling clSetKernelArg.

Fix invalid call to __host__ function in computeBondedForces

Added Integrator.setIntegrationForceGroups()

Made some tests more robust

Cpu generic vector test

Created MTSLangevinIntegrator

Explicitly cast the second parameter to the type of the first one so the compiler can pick an overload that is supported in device code (fixes error: calling a __host__ function("fmin<float, int, (int)0> ") from a __global__ function("computeBondedForces") is not allowed).

Removed name of variadic argument list

This helps pave the way to test wider SIMD ISAs, such as AVX-512.

Naming the argument list of a variadic macro is a GNU extension which is not supported by msvc. Since CUDA uses the system preprocessor this will fail to build kernels on Windows (fixes error C2010: '.': unexpected in macro parameter list).

Replaced alternative spelling of not-operator with '!'

This is required by msvc when standard conformance mode is not enabled (DrudeNoseHooverIntegratorProxy.cpp(53): error C2065: 'not': undeclared identifier).

Bug fix in periodic spline filter (solves #2627)

CPU: Widen mask for exclusion bits (#2676)

The exclusion mask was 8-bits wide, but future CPU support will require
more bits than this (e.g., AVX-512 will be 16-bit).

* Cleaned up checkpointing code for NoseHooverIntegrator

* Fixed compilation error

* Fixed OpenCL compiler errors

* Fixed incorrect references to BAOAB

* Fixed a method that was incorrectly made public

* Convert Nose-Hoover into LF middle scheme by copying NH kernels

* Rebrand VelocityVerletIntegrator as NoseHooverIntegrator

* Consolidate NH tests

* NoseHooverChainKernel begone

* Make Windows builds happy

* Add missing header for Windows build

* Fix mistake in CommonKernels header

* Add 6th Yoshida-Suzuki and make it the default

* CPU: Refactored code to be generic across vector CPU platforms.

Ewald and non-Ewald interactions now share a common code base, templated on
their interaction type.

The vec4 and vec8 implementations have been replaced by a single generic implementation
class which is templated on SIMD type. Currently works for SIMD4 and SIMD8 types, but
can be extended in future to support other types (e.g., AVX-512).

Modified runtime CPU support to lay groundwork for future SIMD types.

Pulled out some vector utility functions (gather pair, reduce),
and refactored the AVX CPU code to make use of them.

* CPU: Fixed coding standards and incorrect header include.

* CPU: Fixed code review comments from PR #2661

* CPU: Fixed CI build issues.

* CPU: Further CI fixes.

* CPU: Fix for unit test failure on MacOS.

Reverted optimised code to go back to a version which is thought to work
on MacOS. The optimisation will be ...

Use coarser granularity to split work in PME kernels

CompoundIntegrator handles checkpoints correctly

Added CI builds for PPC and ARM