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The exclusion mask was 8-bits wide, but future CPU support will require
more bits than this (e.g., AVX-512 will be 16-bit).

* CPU: Refactored code to be generic across vector CPU platforms.

Ewald and non-Ewald interactions now share a common code base, templated on
their interaction type.

The vec4 and vec8 implementations have been replaced by a single generic implementation
class which is templated on SIMD type. Currently works for SIMD4 and SIMD8 types, but
can be extended in future to support other types (e.g., AVX-512).

Modified runtime CPU support to lay groundwork for future SIMD types.

Pulled out some vector utility functions (gather pair, reduce),
and refactored the AVX CPU code to make use of them.

* CPU: Fixed coding standards and incorrect header include.

* CPU: Fixed code review comments from PR #2661

* CPU: Fixed CI build issues.

* CPU: Further CI fixes.

* CPU: Fix for unit test failure on MacOS.

Reverted optimised code to go back to a version which is thought to work
on MacOS. The optimisation will be ...

o Only reference reciprocal space code works, for now.
o Vector lengths of 4 and 8 implemented and tested.
o Tests pass for Reference and CPU platforms.

o Added C12 shift term, to match GMX.
o Added tests to compare energies and forces directly to GMX, with and without exclusions.
o Modified set/get LJPME parameters to look similar to electrostatic equivalents.

o Only reference reciprocal space code works, for now.
o Vector lengths of 4 and 8 implemented and tested.
o Tests pass for Reference and CPU platforms.

o Added C12 shift term, to match GMX.
o Added tests to compare energies and forces directly to GMX, with and without exclusions.
o Modified set/get LJPME parameters to look similar to electrostatic equivalents.