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Commit e472af36 authored by Qianfeng Zhang's avatar Qianfeng Zhang
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Tune the location of a scheduler barrier code line

parent d362410d
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include/ck_tile/ops/fmha/pipeline/block_fmha_pipeline_qr_ks_vs_async.hpp
View file @ e472af36
...@@ -664,9 +664,9 @@ struct BlockFmhaPipelineQRKSVSAsync ...@@ -664,9 +664,9 @@ struct BlockFmhaPipelineQRKSVSAsync
k_tiles[I0] = load_tile(k_dram_window); k_tiles[I0] = load_tile(k_dram_window);
move_tile_window(k_dram_window, {0, kK0}); move_tile_window(k_dram_window, {0, kK0});
}; };
}
__builtin_amdgcn_sched_barrier(0); __builtin_amdgcn_sched_barrier(0);
}
// STAGE 3, KV gemm // STAGE 3, KV gemm
if constexpr(k1_loops > 1) if constexpr(k1_loops > 1)
......
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