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gaoqiong
composable_kernel
Commits
328cc7f4
Commit
328cc7f4
authored
Dec 12, 2022
by
rocking
Browse files
Hard code the vector dim
parent
eead0864
Changes
3
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3 changed files
with
10 additions
and
14 deletions
+10
-14
example/21_gemm_layernorm/gemm_add_add_layernorm_xdl_fp16.cpp
...ple/21_gemm_layernorm/gemm_add_add_layernorm_xdl_fp16.cpp
+5
-5
include/ck/tensor_operation/gpu/device/device_gemm_multiple_d_layernorm_xdl_cshuffle.hpp
.../device/device_gemm_multiple_d_layernorm_xdl_cshuffle.hpp
+1
-3
include/ck/tensor_operation/gpu/grid/gemm_layernorm/gridwise_welford_second_half_layernorm2d.hpp
...mm_layernorm/gridwise_welford_second_half_layernorm2d.hpp
+4
-6
No files found.
example/21_gemm_layernorm/gemm_add_add_layernorm_xdl_fp16.cpp
View file @
328cc7f4
...
@@ -60,11 +60,11 @@ static constexpr auto GemmDefault = ck::tensor_operation::device::GemmSpecializa
...
@@ -60,11 +60,11 @@ static constexpr auto GemmDefault = ck::tensor_operation::device::GemmSpecializa
// clang-format off
// clang-format off
using
DeviceOpInstance
=
ck
::
tensor_operation
::
device
::
DeviceGemmMultipleDLayernorm_Xdl_CShuffle
using
DeviceOpInstance
=
ck
::
tensor_operation
::
device
::
DeviceGemmMultipleDLayernorm_Xdl_CShuffle
//######| ALayout| BLayout| DsLayout| HLayout| AData| BData| AccData| CShuffle| DsData| GammaData| BetaData| HData| A| B| CDE| H| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| PostShuffle| PostShuffle| Layernorm| Layernorm|
Layernorm|
Layernorm| Layernorm| Layernorm| Layernorm|
//######| ALayout| BLayout| DsLayout| HLayout| AData| BData| AccData| CShuffle| DsData| GammaData| BetaData| HData| A| B| CDE| H| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| PostShuffle| PostShuffle| Layernorm| Layernorm| Layernorm| Layernorm| Layernorm| Layernorm|
//######| | | | | Type| Type| Type| DataType| Type| Type| Type| Type| Elementwise| Elementwise| Elementwise| Elementwise| Spacialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| ClusterLengths| ScalarPerVector| ThreadClusterSize| ThreadSliceSize|
ESrcHDst|
ESrc| HDst| GammaSrc| BetaSrc|
//######| | | | | Type| Type| Type| DataType| Type| Type| Type| Type| Elementwise| Elementwise| Elementwise| Elementwise| Spacialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| ClusterLengths| ScalarPerVector| ThreadClusterSize| ThreadSliceSize| ESrc| HDst| GammaSrc| BetaSrc|
//######| | | | | | | | | | | | | Operation| Operation| Operation| Operation| | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _M_N| _M_N| _M_N| _M_N|
VectorDim|
VectorSize| VectorSize| VectorSize| VectorSize|
//######| | | | | | | | | | | | | Operation| Operation| Operation| Operation| | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _M_N| _M_N| _M_N| _M_N| VectorSize| VectorSize| VectorSize| VectorSize|
//######| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
| | | |
//######| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
<
ALayout
,
BLayout
,
DsLayout
,
HLayout
,
ADataType
,
BDataType
,
AccDataType
,
CShuffleDataType
,
DsDataType
,
GammaDataType
,
BetaDataType
,
HDataType
,
AElementOp
,
BElementOp
,
CDEElementOp
,
HElementOp
,
GemmDefault
,
1
,
256
,
256
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
64
,
4
>
,
4
,
S
<
8
,
32
>
,
S
<
1
,
8
>
,
1
,
8
,
8
,
8
,
8
>
;
<
ALayout
,
BLayout
,
DsLayout
,
HLayout
,
ADataType
,
BDataType
,
AccDataType
,
CShuffleDataType
,
DsDataType
,
GammaDataType
,
BetaDataType
,
HDataType
,
AElementOp
,
BElementOp
,
CDEElementOp
,
HElementOp
,
GemmDefault
,
1
,
256
,
256
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
64
,
4
>
,
4
,
S
<
8
,
32
>
,
S
<
1
,
8
>
,
8
,
8
,
8
,
8
>
;
// clang-format on
// clang-format on
auto
f_host_tensor_descriptor1d
=
[](
std
::
size_t
len
,
std
::
size_t
stride
)
{
auto
f_host_tensor_descriptor1d
=
[](
std
::
size_t
len
,
std
::
size_t
stride
)
{
...
...
include/ck/tensor_operation/gpu/device/device_gemm_multiple_d_layernorm_xdl_cshuffle.hpp
View file @
328cc7f4
...
@@ -223,7 +223,6 @@ template <typename ALayout,
...
@@ -223,7 +223,6 @@ template <typename ALayout,
index_t
PostShuffleScalarPerVector
,
index_t
PostShuffleScalarPerVector
,
typename
LayernormThreadClusterSize_M_N
,
typename
LayernormThreadClusterSize_M_N
,
typename
LayernormThreadSliceSize_M_N
,
typename
LayernormThreadSliceSize_M_N
,
index_t
LayernormESrcHDstVectorDim
,
index_t
LayernormESrcVectorSize
,
index_t
LayernormESrcVectorSize
,
index_t
LayernormHDstVectorSize
,
index_t
LayernormHDstVectorSize
,
index_t
LayernormGammaSrcVectorSize
,
index_t
LayernormGammaSrcVectorSize
,
...
@@ -485,7 +484,6 @@ struct DeviceGemmMultipleDLayernorm_Xdl_CShuffle : public BaseOperator
...
@@ -485,7 +484,6 @@ struct DeviceGemmMultipleDLayernorm_Xdl_CShuffle : public BaseOperator
LayernormThreadClusterSize_M_N
::
At
(
I1
),
LayernormThreadClusterSize_M_N
::
At
(
I1
),
LayernormThreadSliceSize_M_N
::
At
(
I0
),
LayernormThreadSliceSize_M_N
::
At
(
I0
),
LayernormThreadSliceSize_M_N
::
At
(
I1
),
LayernormThreadSliceSize_M_N
::
At
(
I1
),
LayernormESrcHDstVectorDim
,
LayernormESrcVectorSize
,
LayernormESrcVectorSize
,
LayernormHDstVectorSize
,
LayernormHDstVectorSize
,
LayernormGammaSrcVectorSize
,
LayernormGammaSrcVectorSize
,
...
@@ -908,7 +906,7 @@ struct DeviceGemmMultipleDLayernorm_Xdl_CShuffle : public BaseOperator
...
@@ -908,7 +906,7 @@ struct DeviceGemmMultipleDLayernorm_Xdl_CShuffle : public BaseOperator
// check vector store of E
// check vector store of E
// only support RowMajor for now
// only support RowMajor for now
if
constexpr
(
is_same_v
<
ELayout
,
Row
>
)
if
constexpr
(
is_same_v
<
ELayout
,
Row
>
&&
is_same_v
<
HLayout
,
Row
>
)
{
{
if
(
arg
.
NRaw_
%
PostShuffleScalarPerVector
!=
0
)
if
(
arg
.
NRaw_
%
PostShuffleScalarPerVector
!=
0
)
{
{
...
...
include/ck/tensor_operation/gpu/grid/gemm_layernorm/gridwise_welford_second_half_layernorm2d.hpp
View file @
328cc7f4
...
@@ -35,20 +35,18 @@ template <typename EDataType,
...
@@ -35,20 +35,18 @@ template <typename EDataType,
index_t
NThreadClusterSize
,
index_t
NThreadClusterSize
,
index_t
MThreadSliceSize
,
index_t
MThreadSliceSize
,
index_t
NThreadSliceSize
,
index_t
NThreadSliceSize
,
index_t
ESrcHDstVectorDim
,
index_t
ESrcVectorSize
,
index_t
ESrcVectorSize
,
index_t
HDstVectorSize
,
index_t
HDstVectorSize
,
index_t
GammaSrcVectorSize
,
index_t
GammaSrcVectorSize
,
index_t
BetaSrcVectorSize
>
index_t
BetaSrcVectorSize
>
struct
GridwiseWelfordSecondHalfLayernorm2d
struct
GridwiseWelfordSecondHalfLayernorm2d
{
{
// TODO - Support ESrcHDstVectorDim == 0
static_assert
(
NThreadSliceSize
%
ESrcVectorSize
==
0
&&
static_assert
(
ESrcHDstVectorDim
==
1
&&
NThreadSliceSize
%
ESrcVectorSize
==
0
&&
NThreadSliceSize
%
GammaSrcVectorSize
==
0
&&
NThreadSliceSize
%
GammaSrcVectorSize
==
0
&&
NThreadSliceSize
%
BetaSrcVectorSize
==
0
,
NThreadSliceSize
%
BetaSrcVectorSize
==
0
,
"Invalid thread slice sizes and/or vector sizes configuration, please check!"
);
"Invalid thread slice sizes and/or vector sizes configuration, please check!"
);
static_assert
(
ESrcHDstVectorDim
==
1
&&
NThreadSliceSize
%
HDstVectorSize
==
0
,
static_assert
(
NThreadSliceSize
%
HDstVectorSize
==
0
,
"Invalid thread slice sizes and/or vector sizes configuration, please check!"
);
"Invalid thread slice sizes and/or vector sizes configuration, please check!"
);
using
ThreadClusterLengths_M_N
=
Sequence
<
MThreadClusterSize
,
NThreadClusterSize
>
;
using
ThreadClusterLengths_M_N
=
Sequence
<
MThreadClusterSize
,
NThreadClusterSize
>
;
...
@@ -227,7 +225,7 @@ struct GridwiseWelfordSecondHalfLayernorm2d
...
@@ -227,7 +225,7 @@ struct GridwiseWelfordSecondHalfLayernorm2d
decltype
(
thread_buffer_desc_m_n
),
decltype
(
thread_buffer_desc_m_n
),
ThreadBufferLengths_M_N
,
ThreadBufferLengths_M_N
,
ThreadBufferDimAccessOrder
,
ThreadBufferDimAccessOrder
,
ESrcHDst
VectorDim
,
1
,
// Src
VectorDim
ESrcVectorSize
,
ESrcVectorSize
,
1
,
1
,
true
>
(
true
>
(
...
@@ -270,7 +268,7 @@ struct GridwiseWelfordSecondHalfLayernorm2d
...
@@ -270,7 +268,7 @@ struct GridwiseWelfordSecondHalfLayernorm2d
HElementwiseOperation
,
HElementwiseOperation
,
ThreadBufferLengths_M_N
,
ThreadBufferLengths_M_N
,
ThreadBufferDimAccessOrder
,
ThreadBufferDimAccessOrder
,
ESrcH
DstVectorDim
,
1
,
//
DstVectorDim
HDstVectorSize
,
HDstVectorSize
,
InMemoryDataOperationEnum
::
Set
,
InMemoryDataOperationEnum
::
Set
,
1
,
1
,
...
...
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