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Commit febc2a3a authored by Antoine Kaufmann's avatar Antoine Kaufmann
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sims: make cpplint happy

parent f722a44f
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Showing with 429 additions and 398 deletions
sims/net/switch/net_switch.cc
View file @ febc2a3a
...@@ -36,8 +36,8 @@ extern "C" { ...@@ -36,8 +36,8 @@ extern "C" {
#include <simbricks/netif/netsim.h> #include <simbricks/netif/netsim.h>
}; };
static uint64_t sync_period = (500 * 1000ULL); // 500ns static uint64_t sync_period = (500 * 1000ULL); // 500ns
static uint64_t eth_latency = (500 * 1000ULL); // 500ns static uint64_t eth_latency = (500 * 1000ULL); // 500ns
/* MAC address type */ /* MAC address type */
struct MAC { struct MAC {
...@@ -56,18 +56,18 @@ struct MAC { ...@@ -56,18 +56,18 @@ struct MAC {
} }
}; };
namespace std { namespace std {
template <> template <>
struct hash<MAC> struct hash<MAC>
{ {
size_t operator()(const MAC &m) const { size_t operator()(const MAC &m) const {
size_t res = 0; size_t res = 0;
for (int i = 0; i < 6; i++) { for (int i = 0; i < 6; i++) {
res = (res << 4) | (res ^ m.data[i]); res = (res << 4) | (res ^ m.data[i]);
} }
return res; return res;
} }
}; };
} // namespace std } // namespace std
/* Global variables */ /* Global variables */
static uint64_t cur_ts = 0; static uint64_t cur_ts = 0;
...@@ -103,7 +103,8 @@ static void forward_pkt(volatile struct cosim_eth_proto_d2n_send *tx, int port) ...@@ -103,7 +103,8 @@ static void forward_pkt(volatile struct cosim_eth_proto_d2n_send *tx, int port)
static void switch_pkt(struct netsim_interface *nsif, int iport) static void switch_pkt(struct netsim_interface *nsif, int iport)
{ {
volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(nsif, cur_ts); volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(nsif,
cur_ts);
if (msg_from == NULL) { if (msg_from == NULL) {
return; return;
} }
......
sims/net/tap/net_tap.c
View file @ febc2a3a
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include <simbricks/netif/netsim.h> #include <simbricks/netif/netsim.h>
//#define DEBUG_PKTMETA // #define DEBUG_PKTMETA
static struct netsim_interface nsif; static struct netsim_interface nsif;
static int tap_fd; static int tap_fd;
......
sims/net/wire/net_wire.c
View file @ febc2a3a
...@@ -38,8 +38,8 @@ ...@@ -38,8 +38,8 @@
#include <simbricks/netif/netsim.h> #include <simbricks/netif/netsim.h>
static uint64_t sync_period = (500 * 1000ULL); // 500ns static uint64_t sync_period = (500 * 1000ULL); // 500ns
static uint64_t eth_latency = (500 * 1000ULL); // 500ns static uint64_t eth_latency = (500 * 1000ULL); // 500ns
static uint64_t cur_ts; static uint64_t cur_ts;
static int exiting = 0; static int exiting = 0;
static pcap_dumper_t *dumpfile = NULL; static pcap_dumper_t *dumpfile = NULL;
...@@ -56,7 +56,8 @@ static void sigusr1_handler(int dummy) ...@@ -56,7 +56,8 @@ static void sigusr1_handler(int dummy)
static void move_pkt(struct netsim_interface *from, struct netsim_interface *to) static void move_pkt(struct netsim_interface *from, struct netsim_interface *to)
{ {
volatile union cosim_eth_proto_d2n *msg_from = netsim_d2n_poll(from, cur_ts); volatile union cosim_eth_proto_d2n *msg_from =
netsim_d2n_poll(from, cur_ts);
volatile union cosim_eth_proto_n2d *msg_to; volatile union cosim_eth_proto_n2d *msg_to;
volatile struct cosim_eth_proto_d2n_send *tx; volatile struct cosim_eth_proto_d2n_send *tx;
volatile struct cosim_eth_proto_n2d_recv *rx; volatile struct cosim_eth_proto_n2d_recv *rx;
...@@ -112,8 +113,8 @@ int main(int argc, char *argv[]) ...@@ -112,8 +113,8 @@ int main(int argc, char *argv[])
int sync_mode = SYNC_MODES; int sync_mode = SYNC_MODES;
if (argc < 3 && argc > 7) { if (argc < 3 && argc > 7) {
fprintf(stderr, "Usage: net_wire SOCKET-A SOCKET-B [SYNC-MODE] [SYNC-PERIOD] " fprintf(stderr, "Usage: net_wire SOCKET-A SOCKET-B [SYNC-MODE] "
"[ETH-LATENCY] [PCAP-FILE]\n"); "[SYNC-PERIOD] [ETH-LATENCY] [PCAP-FILE]\n");
return EXIT_FAILURE; return EXIT_FAILURE;
} }
...@@ -153,11 +154,13 @@ int main(int argc, char *argv[]) ...@@ -153,11 +154,13 @@ int main(int argc, char *argv[])
printf("start polling\n"); printf("start polling\n");
while (!exiting) { while (!exiting) {
if (netsim_n2d_sync(&nsif_a, cur_ts, eth_latency, sync_period, sync_mode) != 0) { if (netsim_n2d_sync(&nsif_a, cur_ts, eth_latency, sync_period,
sync_mode) != 0) {
fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n"); fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n");
abort(); abort();
} }
if (netsim_n2d_sync(&nsif_b, cur_ts, eth_latency, sync_period, sync_mode) != 0) { if (netsim_n2d_sync(&nsif_b, cur_ts, eth_latency, sync_period,
sync_mode) != 0) {
fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n"); fprintf(stderr, "netsim_n2d_sync(nsif_a) failed\n");
abort(); abort();
} }
......
sims/nic/corundum/coord.h
View file @ febc2a3a
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#include <map> #include <map>
#include <iostream> #include <iostream>
#include "debug.h" #include "sims/nic/corundum/debug.h"
class DMAOp; class DMAOp;
struct MMIOOp; struct MMIOOp;
...@@ -68,18 +68,21 @@ class PCICoordinator { ...@@ -68,18 +68,21 @@ class PCICoordinator {
queue.pop_front(); queue.pop_front();
if (op->type == PCIOp::OP_MSI) { if (op->type == PCIOp::OP_MSI) {
#ifdef COORD_DEBUG #ifdef COORD_DEBUG
std::cout << main_time << " issuing msi " << op->msi_vec << std::endl; std::cout << main_time << " issuing msi " << op->msi_vec <<
std::endl;
#endif #endif
pci_msi_issue(op->msi_vec); pci_msi_issue(op->msi_vec);
} else if (op->type == PCIOp::OP_DMA) { } else if (op->type == PCIOp::OP_DMA) {
#ifdef COORD_DEBUG #ifdef COORD_DEBUG
std::cout << main_time << " issuing dma " << op->dma_op << std::endl; std::cout << main_time << " issuing dma " << op->dma_op <<
std::endl;
#endif #endif
pci_dma_issue(op->dma_op); pci_dma_issue(op->dma_op);
dmamap.erase(op->dma_op); dmamap.erase(op->dma_op);
} else if (op->type == PCIOp::OP_RWCOMP) { } else if (op->type == PCIOp::OP_RWCOMP) {
#ifdef COORD_DEBUG #ifdef COORD_DEBUG
std::cout << main_time << " issuing mmio " << op->mmio_op << std::endl; std::cout << main_time << " issuing mmio " << op->mmio_op <<
std::endl;
#endif #endif
pci_rwcomp_issue(op->mmio_op); pci_rwcomp_issue(op->mmio_op);
} else { } else {
...@@ -94,7 +97,8 @@ class PCICoordinator { ...@@ -94,7 +97,8 @@ class PCICoordinator {
void dma_register(DMAOp *dma_op, bool ready) void dma_register(DMAOp *dma_op, bool ready)
{ {
#ifdef COORD_DEBUG #ifdef COORD_DEBUG
std::cout << main_time << " registering dma op " << dma_op << " " << ready << std::endl; std::cout << main_time << " registering dma op " << dma_op << " "
<< ready << std::endl;
#endif #endif
PCIOp *op = new PCIOp; PCIOp *op = new PCIOp;
op->dma_op = dma_op; op->dma_op = dma_op;
...@@ -134,7 +138,8 @@ class PCICoordinator { ...@@ -134,7 +138,8 @@ class PCICoordinator {
void mmio_comp_enqueue(MMIOOp *mmio_op) void mmio_comp_enqueue(MMIOOp *mmio_op)
{ {
#ifdef COORD_DEBUG #ifdef COORD_DEBUG
std::cout << main_time << " enqueuing MMIO comp " << mmio_op << std::endl; std::cout << main_time << " enqueuing MMIO comp " << mmio_op <<
std::endl;
#endif #endif
PCIOp *op = new PCIOp; PCIOp *op = new PCIOp;
op->mmio_op = mmio_op; op->mmio_op = mmio_op;
...@@ -143,10 +148,7 @@ class PCICoordinator { ...@@ -143,10 +148,7 @@ class PCICoordinator {
queue.push_back(op); queue.push_back(op);
process(); process();
} }
}; };
#endif // COORD_H_
#endif
sims/nic/corundum/corundum.h
View file @ febc2a3a
...@@ -25,10 +25,10 @@ ...@@ -25,10 +25,10 @@
#ifndef CORUNDUM_H_ #ifndef CORUNDUM_H_
#define CORUNDUM_H_ #define CORUNDUM_H_
#include "dma.h" #include "sims/nic/corundum/dma.h"
extern uint64_t main_time; extern uint64_t main_time;
void pci_dma_issue(DMAOp *op); void pci_dma_issue(DMAOp *op);
#endif /* ndef CORUNDUM_H_ */ #endif // CORUNDUM_H_
sims/nic/corundum/corundum_verilator.cpp
View file @ febc2a3a
...@@ -27,28 +27,29 @@ ...@@ -27,28 +27,29 @@
#include <set> #include <set>
#include <signal.h> #include <signal.h>
#include <verilated.h>
#ifdef TRACE_ENABLED
#include <verilated_vcd_c.h>
#endif
extern "C" { extern "C" {
#include <simbricks/nicif/nicsim.h> #include <simbricks/nicif/nicsim.h>
} }
#include "Vinterface.h" #include "sims/nic/corundum/obj_dir/Vinterface.h"
#include "verilated.h"
#ifdef TRACE_ENABLED
#include "verilated_vcd_c.h"
#endif
#include "debug.h" #include "sims/nic/corundum/debug.h"
#include "corundum.h" #include "sims/nic/corundum/corundum.h"
#include "coord.h" #include "sims/nic/corundum/coord.h"
#include "dma.h" #include "sims/nic/corundum/dma.h"
#include "mem.h" #include "sims/nic/corundum/mem.h"
struct DMAOp; struct DMAOp;
static uint64_t clock_period = 4 * 1000ULL; // 4ns -> 250MHz static uint64_t clock_period = 4 * 1000ULL; // 4ns -> 250MHz
static uint64_t sync_period = 500 * 1000ULL; // 500ns static uint64_t sync_period = 500 * 1000ULL; // 500ns
static uint64_t pci_latency = 500 * 1000ULL; // 500ns static uint64_t pci_latency = 500 * 1000ULL; // 500ns
static uint64_t eth_latency = 500 * 1000ULL; // 500ns static uint64_t eth_latency = 500 * 1000ULL; // 500ns
...@@ -113,19 +114,19 @@ static void reset_inputs(Vinterface *top) ...@@ -113,19 +114,19 @@ static void reset_inputs(Vinterface *top)
top->m_axil_csr_rresp = 0; top->m_axil_csr_rresp = 0;
top->m_axil_csr_rvalid = 0; top->m_axil_csr_rvalid = 0;
top->ctrl_dma_ram_wr_cmd_sel = 0; top->ctrl_dma_ram_wr_cmd_sel = 0;
//top->ctrl_dma_ram_wr_cmd_be = 0; // top->ctrl_dma_ram_wr_cmd_be = 0;
//top->ctrl_dma_ram_wr_cmd_addr = 0; // top->ctrl_dma_ram_wr_cmd_addr = 0;
top->ctrl_dma_ram_wr_cmd_valid = 0; top->ctrl_dma_ram_wr_cmd_valid = 0;
top->ctrl_dma_ram_rd_cmd_sel = 0; top->ctrl_dma_ram_rd_cmd_sel = 0;
//top->ctrl_dma_ram_rd_cmd_addr = 0; // top->ctrl_dma_ram_rd_cmd_addr = 0;
top->ctrl_dma_ram_rd_cmd_valid = 0; top->ctrl_dma_ram_rd_cmd_valid = 0;
top->ctrl_dma_ram_rd_resp_ready = 0; top->ctrl_dma_ram_rd_resp_ready = 0;
top->data_dma_ram_wr_cmd_sel = 0; top->data_dma_ram_wr_cmd_sel = 0;
//top->data_dma_ram_wr_cmd_be = 0; // top->data_dma_ram_wr_cmd_be = 0;
//top->data_dma_ram_wr_cmd_addr = 0; // top->data_dma_ram_wr_cmd_addr = 0;
top->data_dma_ram_wr_cmd_valid = 0; top->data_dma_ram_wr_cmd_valid = 0;
top->data_dma_ram_rd_cmd_sel = 0; top->data_dma_ram_rd_cmd_sel = 0;
//top->data_dma_ram_rd_cmd_addr = 0; // top->data_dma_ram_rd_cmd_addr = 0;
top->data_dma_ram_rd_cmd_valid = 0; top->data_dma_ram_rd_cmd_valid = 0;
top->data_dma_ram_rd_resp_ready = 0; top->data_dma_ram_rd_resp_ready = 0;
top->tx_axis_tready = 0; top->tx_axis_tready = 0;
...@@ -148,30 +149,54 @@ static void report_output(const char *label, uint64_t val) ...@@ -148,30 +149,54 @@ static void report_output(const char *label, uint64_t val)
static void report_outputs(Vinterface *top) static void report_outputs(Vinterface *top)
{ {
report_output("m_axis_ctrl_dma_read_desc_dma_addr", top->m_axis_ctrl_dma_read_desc_dma_addr); report_output("m_axis_ctrl_dma_read_desc_dma_addr",
report_output("m_axis_ctrl_dma_read_desc_ram_sel", top->m_axis_ctrl_dma_read_desc_ram_sel); top->m_axis_ctrl_dma_read_desc_dma_addr);
report_output("m_axis_ctrl_dma_read_desc_ram_addr", top->m_axis_ctrl_dma_read_desc_ram_addr); report_output("m_axis_ctrl_dma_read_desc_ram_sel",
report_output("m_axis_ctrl_dma_read_desc_len", top->m_axis_ctrl_dma_read_desc_len); top->m_axis_ctrl_dma_read_desc_ram_sel);
report_output("m_axis_ctrl_dma_read_desc_tag", top->m_axis_ctrl_dma_read_desc_tag); report_output("m_axis_ctrl_dma_read_desc_ram_addr",
report_output("m_axis_ctrl_dma_read_desc_valid", top->m_axis_ctrl_dma_read_desc_valid); top->m_axis_ctrl_dma_read_desc_ram_addr);
report_output("m_axis_ctrl_dma_write_desc_dma_addr", top->m_axis_ctrl_dma_write_desc_dma_addr); report_output("m_axis_ctrl_dma_read_desc_len",
report_output("m_axis_ctrl_dma_write_desc_ram_sel", top->m_axis_ctrl_dma_write_desc_ram_sel); top->m_axis_ctrl_dma_read_desc_len);
report_output("m_axis_ctrl_dma_write_desc_ram_addr", top->m_axis_ctrl_dma_write_desc_ram_addr); report_output("m_axis_ctrl_dma_read_desc_tag",
report_output("m_axis_ctrl_dma_write_desc_len", top->m_axis_ctrl_dma_write_desc_len); top->m_axis_ctrl_dma_read_desc_tag);
report_output("m_axis_ctrl_dma_write_desc_tag", top->m_axis_ctrl_dma_write_desc_tag); report_output("m_axis_ctrl_dma_read_desc_valid",
report_output("m_axis_ctrl_dma_write_desc_valid", top->m_axis_ctrl_dma_write_desc_valid); top->m_axis_ctrl_dma_read_desc_valid);
report_output("m_axis_data_dma_read_desc_dma_addr", top->m_axis_data_dma_read_desc_dma_addr); report_output("m_axis_ctrl_dma_write_desc_dma_addr",
report_output("m_axis_data_dma_read_desc_ram_sel", top->m_axis_data_dma_read_desc_ram_sel); top->m_axis_ctrl_dma_write_desc_dma_addr);
report_output("m_axis_data_dma_read_desc_ram_addr", top->m_axis_data_dma_read_desc_ram_addr); report_output("m_axis_ctrl_dma_write_desc_ram_sel",
report_output("m_axis_data_dma_read_desc_len", top->m_axis_data_dma_read_desc_len); top->m_axis_ctrl_dma_write_desc_ram_sel);
report_output("m_axis_data_dma_read_desc_tag", top->m_axis_data_dma_read_desc_tag); report_output("m_axis_ctrl_dma_write_desc_ram_addr",
report_output("m_axis_data_dma_read_desc_valid", top->m_axis_data_dma_read_desc_valid); top->m_axis_ctrl_dma_write_desc_ram_addr);
report_output("m_axis_data_dma_write_desc_dma_addr", top->m_axis_data_dma_write_desc_dma_addr); report_output("m_axis_ctrl_dma_write_desc_len",
report_output("m_axis_data_dma_write_desc_ram_sel", top->m_axis_data_dma_write_desc_ram_sel); top->m_axis_ctrl_dma_write_desc_len);
report_output("m_axis_data_dma_write_desc_ram_addr", top->m_axis_data_dma_write_desc_ram_addr); report_output("m_axis_ctrl_dma_write_desc_tag",
report_output("m_axis_data_dma_write_desc_len", top->m_axis_data_dma_write_desc_len); top->m_axis_ctrl_dma_write_desc_tag);
report_output("m_axis_data_dma_write_desc_tag", top->m_axis_data_dma_write_desc_tag); report_output("m_axis_ctrl_dma_write_desc_valid",
report_output("m_axis_data_dma_write_desc_valid", top->m_axis_data_dma_write_desc_valid); top->m_axis_ctrl_dma_write_desc_valid);
report_output("m_axis_data_dma_read_desc_dma_addr",
top->m_axis_data_dma_read_desc_dma_addr);
report_output("m_axis_data_dma_read_desc_ram_sel",
top->m_axis_data_dma_read_desc_ram_sel);
report_output("m_axis_data_dma_read_desc_ram_addr",
top->m_axis_data_dma_read_desc_ram_addr);
report_output("m_axis_data_dma_read_desc_len",
top->m_axis_data_dma_read_desc_len);
report_output("m_axis_data_dma_read_desc_tag",
top->m_axis_data_dma_read_desc_tag);
report_output("m_axis_data_dma_read_desc_valid",
top->m_axis_data_dma_read_desc_valid);
report_output("m_axis_data_dma_write_desc_dma_addr",
top->m_axis_data_dma_write_desc_dma_addr);
report_output("m_axis_data_dma_write_desc_ram_sel",
top->m_axis_data_dma_write_desc_ram_sel);
report_output("m_axis_data_dma_write_desc_ram_addr",
top->m_axis_data_dma_write_desc_ram_addr);
report_output("m_axis_data_dma_write_desc_len",
top->m_axis_data_dma_write_desc_len);
report_output("m_axis_data_dma_write_desc_tag",
top->m_axis_data_dma_write_desc_tag);
report_output("m_axis_data_dma_write_desc_valid",
top->m_axis_data_dma_write_desc_valid);
report_output("s_axil_awready", top->s_axil_awready); report_output("s_axil_awready", top->s_axil_awready);
report_output("s_axil_wready", top->s_axil_wready); report_output("s_axil_wready", top->s_axil_wready);
report_output("s_axil_bresp", top->s_axil_bresp); report_output("s_axil_bresp", top->s_axil_bresp);
...@@ -193,10 +218,12 @@ static void report_outputs(Vinterface *top) ...@@ -193,10 +218,12 @@ static void report_outputs(Vinterface *top)
report_output("m_axil_csr_rready", top->m_axil_csr_rready); report_output("m_axil_csr_rready", top->m_axil_csr_rready);
report_output("ctrl_dma_ram_wr_cmd_ready", top->ctrl_dma_ram_wr_cmd_ready); report_output("ctrl_dma_ram_wr_cmd_ready", top->ctrl_dma_ram_wr_cmd_ready);
report_output("ctrl_dma_ram_rd_cmd_ready", top->ctrl_dma_ram_rd_cmd_ready); report_output("ctrl_dma_ram_rd_cmd_ready", top->ctrl_dma_ram_rd_cmd_ready);
report_output("ctrl_dma_ram_rd_resp_valid", top->ctrl_dma_ram_rd_resp_valid); report_output("ctrl_dma_ram_rd_resp_valid",
top->ctrl_dma_ram_rd_resp_valid);
report_output("data_dma_ram_wr_cmd_ready", top->data_dma_ram_wr_cmd_ready); report_output("data_dma_ram_wr_cmd_ready", top->data_dma_ram_wr_cmd_ready);
report_output("data_dma_ram_rd_cmd_ready", top->data_dma_ram_rd_cmd_ready); report_output("data_dma_ram_rd_cmd_ready", top->data_dma_ram_rd_cmd_ready);
report_output("data_dma_ram_rd_resp_valid", top->data_dma_ram_rd_resp_valid); report_output("data_dma_ram_rd_resp_valid",
top->data_dma_ram_rd_resp_valid);
report_output("tx_axis_tkeep", top->tx_axis_tkeep); report_output("tx_axis_tkeep", top->tx_axis_tkeep);
report_output("tx_axis_tvalid", top->tx_axis_tvalid); report_output("tx_axis_tvalid", top->tx_axis_tvalid);
report_output("tx_axis_tlast", top->tx_axis_tlast); report_output("tx_axis_tlast", top->tx_axis_tlast);
...@@ -217,7 +244,6 @@ struct MMIOOp { ...@@ -217,7 +244,6 @@ struct MMIOOp {
class MMIOInterface { class MMIOInterface {
protected: protected:
enum OpState { enum OpState {
AddrIssued, AddrIssued,
AddrAcked, AddrAcked,
...@@ -252,8 +278,8 @@ class MMIOInterface { ...@@ -252,8 +278,8 @@ class MMIOInterface {
rCur->value = top.s_axil_rdata; rCur->value = top.s_axil_rdata;
coord.mmio_comp_enqueue(rCur); coord.mmio_comp_enqueue(rCur);
#ifdef MMIO_DEBUG #ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: completed AXI read op=" << rCur << " val=" << std::cout << main_time << " MMIO: completed AXI read op=" <<
rCur->value << std::endl; rCur << " val=" << rCur->value << std::endl;
#endif #endif
rCur = 0; rCur = 0;
} }
...@@ -274,10 +300,10 @@ class MMIOInterface { ...@@ -274,10 +300,10 @@ class MMIOInterface {
if (wState == AddrDone && top.s_axil_bvalid) { if (wState == AddrDone && top.s_axil_bvalid) {
/* write complete */ /* write complete */
top.s_axil_bready = 0; top.s_axil_bready = 0;
// TODO: check top.s_axil_bresp // TODO(antoinek): check top.s_axil_bresp
#ifdef MMIO_DEBUG #ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: completed AXI write op=" << wCur << std::cout << main_time << " MMIO: completed AXI write op="
std::endl; << wCur << std::endl;
#endif #endif
coord.mmio_comp_enqueue(wCur); coord.mmio_comp_enqueue(wCur);
wCur = 0; wCur = 0;
...@@ -310,7 +336,6 @@ class MMIOInterface { ...@@ -310,7 +336,6 @@ class MMIOInterface {
top.s_axil_wdata = wCur->value; top.s_axil_wdata = wCur->value;
top.s_axil_wstrb = 0xf; top.s_axil_wstrb = 0xf;
top.s_axil_wvalid = 1; top.s_axil_wvalid = 1;
} }
} }
} }
...@@ -319,8 +344,8 @@ class MMIOInterface { ...@@ -319,8 +344,8 @@ class MMIOInterface {
{ {
MMIOOp *op = new MMIOOp; MMIOOp *op = new MMIOOp;
#ifdef MMIO_DEBUG #ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: read id=" << id << " addr=" << std::hex << addr std::cout << main_time << " MMIO: read id=" << id << " addr=" <<
<< " len=" << len << " op=" << op << std::endl; std::hex << addr << " len=" << len << " op=" << op << std::endl;
#endif #endif
op->id = id; op->id = id;
op->addr = addr; op->addr = addr;
...@@ -334,8 +359,9 @@ class MMIOInterface { ...@@ -334,8 +359,9 @@ class MMIOInterface {
{ {
MMIOOp *op = new MMIOOp; MMIOOp *op = new MMIOOp;
#ifdef MMIO_DEBUG #ifdef MMIO_DEBUG
std::cout << main_time << " MMIO: write id=" << id << " addr=" << std::hex << addr std::cout << main_time << " MMIO: write id=" << id << " addr=" <<
<< " len=" << len << " val=" << val << " op=" << op << std::endl; std::hex << addr << " len=" << len << " val=" << val << " op="
<< op << std::endl;
#endif #endif
op->id = id; op->id = id;
op->addr = addr; op->addr = addr;
...@@ -344,7 +370,6 @@ class MMIOInterface { ...@@ -344,7 +370,6 @@ class MMIOInterface {
op->isWrite = true; op->isWrite = true;
queue.push_back(op); queue.push_back(op);
} }
}; };
void pci_rwcomp_issue(MMIOOp *op) void pci_rwcomp_issue(MMIOOp *op)
...@@ -360,7 +385,7 @@ void pci_rwcomp_issue(MMIOOp *op) ...@@ -360,7 +385,7 @@ void pci_rwcomp_issue(MMIOOp *op)
wc = &msg->writecomp; wc = &msg->writecomp;
wc->req_id = op->id; wc->req_id = op->id;
//WMB(); // WMB();
wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST; COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else { } else {
...@@ -368,7 +393,7 @@ void pci_rwcomp_issue(MMIOOp *op) ...@@ -368,7 +393,7 @@ void pci_rwcomp_issue(MMIOOp *op)
memcpy((void *) rc->data, &op->value, op->len); memcpy((void *) rc->data, &op->value, op->len);
rc->req_id = op->id; rc->req_id = op->id;
//WMB(); // WMB();
rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP | rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST; COSIM_PCIE_PROTO_D2H_OWN_HOST;
} }
...@@ -435,7 +460,7 @@ void pci_dma_issue(DMAOp *op) ...@@ -435,7 +460,7 @@ void pci_dma_issue(DMAOp *op)
write->offset = op->dma_addr; write->offset = op->dma_addr;
write->len = op->len; write->len = op->len;
// TODO: check DMA length // TODO(antoinek): check DMA length
memcpy((void *) write->data, op->data, op->len); memcpy((void *) write->data, op->data, op->len);
// WMB(); // WMB();
...@@ -513,7 +538,7 @@ static void csr_write(uint64_t off, uint64_t val) ...@@ -513,7 +538,7 @@ static void csr_write(uint64_t off, uint64_t val)
static void h2d_read(MMIOInterface &mmio, static void h2d_read(MMIOInterface &mmio,
volatile struct cosim_pcie_proto_h2d_read *read) volatile struct cosim_pcie_proto_h2d_read *read)
{ {
//std::cout << "got read " << read->offset << std::endl; // std::cout << "got read " << read->offset << std::endl;
if (read->offset < 0x80000) { if (read->offset < 0x80000) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc(); volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
volatile struct cosim_pcie_proto_d2h_readcomp *rc; volatile struct cosim_pcie_proto_d2h_readcomp *rc;
...@@ -527,7 +552,7 @@ static void h2d_read(MMIOInterface &mmio, ...@@ -527,7 +552,7 @@ static void h2d_read(MMIOInterface &mmio,
memcpy((void *) rc->data, &val, read->len); memcpy((void *) rc->data, &val, read->len);
rc->req_id = read->req_id; rc->req_id = read->req_id;
//WMB(); // WMB();
rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP | rc->own_type = COSIM_PCIE_PROTO_D2H_MSG_READCOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST; COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else { } else {
...@@ -544,7 +569,7 @@ static void h2d_write(MMIOInterface &mmio, ...@@ -544,7 +569,7 @@ static void h2d_write(MMIOInterface &mmio,
memcpy(&val, (void *) write->data, write->len); memcpy(&val, (void *) write->data, write->len);
//std::cout << "got write " << write->offset << " = " << val << std::endl; // std::cout << "got write " << write->offset << " = " << val << std::endl;
if (write->offset < 0x80000) { if (write->offset < 0x80000) {
volatile union cosim_pcie_proto_d2h *msg = d2h_alloc(); volatile union cosim_pcie_proto_d2h *msg = d2h_alloc();
...@@ -558,7 +583,7 @@ static void h2d_write(MMIOInterface &mmio, ...@@ -558,7 +583,7 @@ static void h2d_write(MMIOInterface &mmio,
wc = &msg->writecomp; wc = &msg->writecomp;
wc->req_id = write->req_id; wc->req_id = write->req_id;
//WMB(); // WMB();
wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP | wc->own_type = COSIM_PCIE_PROTO_D2H_MSG_WRITECOMP |
COSIM_PCIE_PROTO_D2H_OWN_HOST; COSIM_PCIE_PROTO_D2H_OWN_HOST;
} else { } else {
...@@ -577,7 +602,7 @@ static void poll_h2d(MMIOInterface &mmio) ...@@ -577,7 +602,7 @@ static void poll_h2d(MMIOInterface &mmio)
t = msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK; t = msg->dummy.own_type & COSIM_PCIE_PROTO_H2D_MSG_MASK;
//std::cerr << "poll_h2d: polled type=" << (int) t << std::endl; // std::cerr << "poll_h2d: polled type=" << (int) t << std::endl;
switch (t) { switch (t) {
case COSIM_PCIE_PROTO_H2D_MSG_READ: case COSIM_PCIE_PROTO_H2D_MSG_READ:
h2d_read(mmio, &msg->read); h2d_read(mmio, &msg->read);
...@@ -607,7 +632,6 @@ static void poll_h2d(MMIOInterface &mmio) ...@@ -607,7 +632,6 @@ static void poll_h2d(MMIOInterface &mmio)
nicif_h2d_done(msg); nicif_h2d_done(msg);
nicif_h2d_next(); nicif_h2d_next();
}; };
static volatile union cosim_pcie_proto_d2h *d2h_alloc(void) static volatile union cosim_pcie_proto_d2h *d2h_alloc(void)
...@@ -641,12 +665,13 @@ class EthernetTx { ...@@ -641,12 +665,13 @@ class EthernetTx {
send->len = packet_len; send->len = packet_len;
send->timestamp = main_time + eth_latency; send->timestamp = main_time + eth_latency;
//WMB(); // WMB();
send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND | send->own_type = COSIM_ETH_PROTO_D2N_MSG_SEND |
COSIM_ETH_PROTO_D2N_OWN_NET; COSIM_ETH_PROTO_D2N_OWN_NET;
#ifdef ETH_DEBUG #ifdef ETH_DEBUG
std::cerr << main_time << " EthernetTx: packet len=" << std::hex << packet_len << " "; std::cerr << main_time << " EthernetTx: packet len=" << std::hex <<
packet_len << " ";
for (size_t i = 0; i < packet_len; i++) { for (size_t i = 0; i < packet_len; i++) {
std::cerr << (unsigned) packet_buf[i] << " "; std::cerr << (unsigned) packet_buf[i] << " ";
} }
...@@ -663,7 +688,8 @@ class EthernetTx { ...@@ -663,7 +688,8 @@ class EthernetTx {
for (size_t i = 0; i < 8; i++) { for (size_t i = 0; i < 8; i++) {
if ((top.tx_axis_tkeep & (1 << i)) != 0) { if ((top.tx_axis_tkeep & (1 << i)) != 0) {
assert(packet_len < 2048); assert(packet_len < 2048);
packet_buf[packet_len++] = (top.tx_axis_tdata >> (i * 8)); packet_buf[packet_len++] =
(top.tx_axis_tdata >> (i * 8));
} }
} }
...@@ -708,7 +734,8 @@ class EthernetRx { ...@@ -708,7 +734,8 @@ class EthernetRx {
#ifdef ETH_DEBUG #ifdef ETH_DEBUG
std::cout << main_time << " rx into " << fifo_pos_wr << std::endl; std::cout << main_time << " rx into " << fifo_pos_wr << std::endl;
std::cerr << main_time << " EthernetRx: packet len=" << std::hex << len << " "; std::cerr << main_time << " EthernetRx: packet len=" << std::hex <<
len << " ";
for (size_t i = 0; i < len; i++) { for (size_t i = 0; i < len; i++) {
std::cerr << (unsigned) fifo_bufs[fifo_pos_wr][i] << " "; std::cerr << (unsigned) fifo_bufs[fifo_pos_wr][i] << " ";
} }
...@@ -728,7 +755,8 @@ class EthernetRx { ...@@ -728,7 +755,8 @@ class EthernetRx {
} else if (packet_off == fifo_lens[fifo_pos_rd]) { } else if (packet_off == fifo_lens[fifo_pos_rd]) {
// done with packet // done with packet
#ifdef ETH_DEBUG #ifdef ETH_DEBUG
std::cerr << main_time << " EthernetRx: finished packet" << std::endl; std::cerr << main_time << " EthernetRx: finished packet" <<
std::endl;
#endif #endif
top.rx_axis_tvalid = 0; top.rx_axis_tvalid = 0;
top.rx_axis_tlast = 0; top.rx_axis_tlast = 0;
...@@ -739,14 +767,16 @@ class EthernetRx { ...@@ -739,14 +767,16 @@ class EthernetRx {
} else { } else {
// put out more packet data // put out more packet data
#ifdef ETH_DEBUG #ifdef ETH_DEBUG
std::cerr << main_time << " EthernetRx: push flit " << packet_off << std::endl; std::cerr << main_time << " EthernetRx: push flit " <<
packet_off << std::endl;
if (packet_off == 0) if (packet_off == 0)
std::cout << "rx from " << fifo_pos_rd << std::endl; std::cout << "rx from " << fifo_pos_rd << std::endl;
#endif #endif
top.rx_axis_tkeep = 0; top.rx_axis_tkeep = 0;
top.rx_axis_tdata = 0; top.rx_axis_tdata = 0;
size_t i; size_t i;
for (i = 0; i < 8 && packet_off < fifo_lens[fifo_pos_rd]; i++) { for (i = 0; i < 8 && packet_off < fifo_lens[fifo_pos_rd];
i++) {
top.rx_axis_tdata |= top.rx_axis_tdata |=
((uint64_t) fifo_bufs[fifo_pos_rd][packet_off]) << ((uint64_t) fifo_bufs[fifo_pos_rd][packet_off]) <<
(i * 8); (i * 8);
...@@ -756,14 +786,13 @@ class EthernetRx { ...@@ -756,14 +786,13 @@ class EthernetRx {
top.rx_axis_tvalid = 1; top.rx_axis_tvalid = 1;
top.rx_axis_tlast = (packet_off == fifo_lens[fifo_pos_rd]); top.rx_axis_tlast = (packet_off == fifo_lens[fifo_pos_rd]);
} }
//trace->dump(main_time); // trace->dump(main_time);
} else { } else {
// no data // no data
top.rx_axis_tvalid = 0; top.rx_axis_tvalid = 0;
top.rx_axis_tlast = 0; top.rx_axis_tlast = 0;
} }
} }
}; };
static void n2d_recv(EthernetRx &rx, static void n2d_recv(EthernetRx &rx,
...@@ -899,7 +928,8 @@ static void msi_step(Vinterface &top, PCICoordinator &coord) ...@@ -899,7 +928,8 @@ static void msi_step(Vinterface &top, PCICoordinator &coord)
return; return;
#ifdef MSI_DEBUG #ifdef MSI_DEBUG
std::cerr << main_time << " msi_step: MSI interrupt raw vec=" << (int) top.msi_irq << std::endl; std::cerr << main_time << " msi_step: MSI interrupt raw vec=" <<
(int) top.msi_irq << std::endl;
#endif #endif
for (size_t i = 0; i < 32; i++) { for (size_t i = 0; i < 32; i++) {
if (!((1ULL << i) & top.msi_irq)) if (!((1ULL << i) & top.msi_irq))
...@@ -919,8 +949,8 @@ int main(int argc, char *argv[]) ...@@ -919,8 +949,8 @@ int main(int argc, char *argv[])
if (argc < 4 && argc > 10) { if (argc < 4 && argc > 10) {
fprintf(stderr, "Usage: corundum_verilator PCI-SOCKET ETH-SOCKET " fprintf(stderr, "Usage: corundum_verilator PCI-SOCKET ETH-SOCKET "
"SHM [SYNC-MODE] [START-TICK] [SYNC-PERIOD] [PCI-LATENCY] [ETH-LATENCY] " "SHM [SYNC-MODE] [START-TICK] [SYNC-PERIOD] [PCI-LATENCY] "
"[CLOCK-FREQ-MHZ]\n"); "[ETH-LATENCY] [CLOCK-FREQ-MHZ]\n");
return EXIT_FAILURE; return EXIT_FAILURE;
} }
if (argc >= 5) if (argc >= 5)
...@@ -1049,7 +1079,7 @@ int main(int argc, char *argv[]) ...@@ -1049,7 +1079,7 @@ int main(int argc, char *argv[])
top->s_axis_data_dma_write_desc_status_tag, top->s_axis_data_dma_write_desc_status_tag,
top->s_axis_data_dma_write_desc_status_valid); top->s_axis_data_dma_write_desc_status_valid);
//PCICoordinator pci_coord; // PCICoordinator pci_coord;
PCICoordinator pci_coord_mmio; PCICoordinator pci_coord_mmio;
PCICoordinator pci_coord_msi; PCICoordinator pci_coord_msi;
PCICoordinator pci_coord_rc; PCICoordinator pci_coord_rc;
...@@ -1063,10 +1093,14 @@ int main(int argc, char *argv[]) ...@@ -1063,10 +1093,14 @@ int main(int argc, char *argv[])
MemWriter mem_data_writer(p_mem_write_data_dma); MemWriter mem_data_writer(p_mem_write_data_dma);
MemReader mem_data_reader(p_mem_read_data_dma); MemReader mem_data_reader(p_mem_read_data_dma);
DMAReader dma_read_ctrl("read ctrl", p_dma_read_ctrl, mem_control_writer, pci_coord_rc); DMAReader dma_read_ctrl("read ctrl", p_dma_read_ctrl, mem_control_writer,
DMAWriter dma_write_ctrl("write ctrl", p_dma_write_ctrl, mem_control_reader, pci_coord_wc); pci_coord_rc);
DMAReader dma_read_data("read data", p_dma_read_data, mem_data_writer, pci_coord_rd); DMAWriter dma_write_ctrl("write ctrl", p_dma_write_ctrl, mem_control_reader,
DMAWriter dma_write_data("write data", p_dma_write_data, mem_data_reader, pci_coord_wd); pci_coord_wc);
DMAReader dma_read_data("read data", p_dma_read_data, mem_data_writer,
pci_coord_rd);
DMAWriter dma_write_data("write data", p_dma_write_data, mem_data_reader,
pci_coord_wd);
EthernetTx tx(*top); EthernetTx tx(*top);
EthernetRx rx(*top); EthernetRx rx(*top);
...@@ -1120,14 +1154,15 @@ int main(int argc, char *argv[]) ...@@ -1120,14 +1154,15 @@ int main(int argc, char *argv[])
top->clk = !top->clk; top->clk = !top->clk;
main_time += clock_period / 2; main_time += clock_period / 2;
//top->s_axis_tx_ptp_ts_96 = main_time; // top->s_axis_tx_ptp_ts_96 = main_time;
top->s_axis_tx_ptp_ts_valid = 1; top->s_axis_tx_ptp_ts_valid = 1;
top->s_axis_rx_ptp_ts_valid = 1; top->s_axis_rx_ptp_ts_valid = 1;
top->eval(); top->eval();
} }
report_outputs(top); report_outputs(top);
std::cout << std::endl << std::endl << "main_time:" << main_time << std::endl; std::cout << std::endl << std::endl << "main_time:" << main_time <<
std::endl;
#ifdef TRACE_ENABLED #ifdef TRACE_ENABLED
trace->dump(main_time + 1); trace->dump(main_time + 1);
......
sims/nic/corundum/debug.h
View file @ febc2a3a
...@@ -22,9 +22,14 @@ ...@@ -22,9 +22,14 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ */
//#define COORD_DEBUG 1 #ifndef DEBUG_H_
//#define ETH_DEBUG 1 #define DEBUG_H_
//#define MSI_DEBUG 1
//#define DMA_DEBUG 1 // #define COORD_DEBUG 1
//#define MEM_DEBUG 1 // #define ETH_DEBUG 1
//#define MMIO_DEBUG 1 // #define MSI_DEBUG 1
// #define DMA_DEBUG 1
// #define MEM_DEBUG 1
// #define MMIO_DEBUG 1
#endif // DEBUG_H_
sims/nic/corundum/dma.cpp
View file @ febc2a3a
...@@ -24,10 +24,10 @@ ...@@ -24,10 +24,10 @@
#include <iostream> #include <iostream>
#include "debug.h" #include "sims/nic/corundum/debug.h"
#include "corundum.h" #include "sims/nic/corundum/corundum.h"
#include "dma.h" #include "sims/nic/corundum/dma.h"
#include "mem.h" #include "sims/nic/corundum/mem.h"
void DMAReader::step() void DMAReader::step()
...@@ -45,8 +45,8 @@ void DMAReader::step() ...@@ -45,8 +45,8 @@ void DMAReader::step()
pending.insert(op); pending.insert(op);
#ifdef DMA_DEBUG #ifdef DMA_DEBUG
std::cout << main_time << " dma[" << label << "] op " << std::hex << op->dma_addr << " -> " << std::cout << main_time << " dma[" << label << "] op " << std::hex <<
op->ram_sel << ":" << op->ram_addr << op->dma_addr << " -> " << op->ram_sel << ":" << op->ram_addr <<
" len=" << op->len << " tag=" << (int) op->tag << std::endl; " len=" << op->len << " tag=" << (int) op->tag << std::endl;
#endif #endif
...@@ -58,7 +58,8 @@ void DMAReader::step() ...@@ -58,7 +58,8 @@ void DMAReader::step()
DMAOp *op = completed.front(); DMAOp *op = completed.front();
completed.pop_front(); completed.pop_front();
//std::cout << "dma[" << label << "] status complete " << op->dma_addr << std::endl; // std::cout << "dma[" << label << "] status complete " << op->dma_addr
// << std::endl;
p.dma_status_valid = 1; p.dma_status_valid = 1;
p.dma_status_tag = op->tag; p.dma_status_tag = op->tag;
...@@ -75,7 +76,8 @@ void DMAReader::pci_op_complete(DMAOp *op) ...@@ -75,7 +76,8 @@ void DMAReader::pci_op_complete(DMAOp *op)
void DMAReader::mem_op_complete(DMAOp *op) void DMAReader::mem_op_complete(DMAOp *op)
{ {
completed.push_back(op); completed.push_back(op);
//std::cout << "dma[" << label << "] mem complete " << op->dma_addr << std::endl; // std::cout << "dma[" << label << "] mem complete " << op->dma_addr <<
// std::endl;
} }
...@@ -95,9 +97,10 @@ void DMAWriter::step() ...@@ -95,9 +97,10 @@ void DMAWriter::step()
pending.insert(op); pending.insert(op);
#ifdef DMA_DEBUG #ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] op " << std::hex << op->dma_addr << " -> " << std::cout << main_time << " dma write [" << label << "] op " <<
op->ram_sel << ":" << op->ram_addr << std::hex << op->dma_addr << " -> " << op->ram_sel << ":" <<
" len=" << op->len << " tag=" << (int) op->tag << std::endl; op->ram_addr << " len=" << op->len << " tag=" << (int) op->tag
<< std::endl;
#endif #endif
coord.dma_register(op, false); coord.dma_register(op, false);
...@@ -110,13 +113,14 @@ void DMAWriter::step() ...@@ -110,13 +113,14 @@ void DMAWriter::step()
completed.pop_front(); completed.pop_front();
#ifdef DMA_DEBUG #ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] status complete " << op->dma_addr << std::endl; std::cout << main_time << " dma write [" << label <<
"] status complete " << op->dma_addr << std::endl;
#endif #endif
p.dma_status_valid = 1; p.dma_status_valid = 1;
p.dma_status_tag = op->tag; p.dma_status_tag = op->tag;
pending.erase(op); pending.erase(op);
//coord.msi_enqueue(0); // coord.msi_enqueue(0);
delete op; delete op;
} }
} }
...@@ -124,7 +128,8 @@ void DMAWriter::step() ...@@ -124,7 +128,8 @@ void DMAWriter::step()
void DMAWriter::pci_op_complete(DMAOp *op) void DMAWriter::pci_op_complete(DMAOp *op)
{ {
#ifdef DMA_DEBUG #ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] pci complete " << op->dma_addr << std::endl; std::cout << main_time << " dma write [" << label << "] pci complete " <<
op->dma_addr << std::endl;
#endif #endif
completed.push_back(op); completed.push_back(op);
} }
...@@ -132,7 +137,8 @@ void DMAWriter::pci_op_complete(DMAOp *op) ...@@ -132,7 +137,8 @@ void DMAWriter::pci_op_complete(DMAOp *op)
void DMAWriter::mem_op_complete(DMAOp *op) void DMAWriter::mem_op_complete(DMAOp *op)
{ {
#ifdef DMA_DEBUG #ifdef DMA_DEBUG
std::cout << main_time << " dma write [" << label << "] mem complete " << op->dma_addr << ": "; std::cout << main_time << " dma write [" << label << "] mem complete " <<
op->dma_addr << ": ";
for (size_t i = 0; i < op->len; i++) for (size_t i = 0; i < op->len; i++)
std::cout << (unsigned) op->data[i] << " "; std::cout << (unsigned) op->data[i] << " ";
std::cout << std::endl; std::cout << std::endl;
......
sims/nic/corundum/dma.h
View file @ febc2a3a
...@@ -22,17 +22,18 @@ ...@@ -22,17 +22,18 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ */
#ifndef MEM_H_ #ifndef DMA_H_
#define MEM_H_ #define DMA_H_
#include <set> #include <set>
#include <deque> #include <deque>
#include "Vinterface.h" #include <verilated.h>
#include "verilated.h"
#include "debug.h" #include "sims/nic/corundum/obj_dir/Vinterface.h"
#include "coord.h"
#include "sims/nic/corundum/debug.h"
#include "sims/nic/corundum/coord.h"
#define MAX_DMA_LEN 2048 #define MAX_DMA_LEN 2048
...@@ -132,4 +133,4 @@ class DMAWriter : public DMAEngine { ...@@ -132,4 +133,4 @@ class DMAWriter : public DMAEngine {
}; };
#endif /* ndef DMA_H_ */ #endif // DMA_H_
sims/nic/corundum/mem.cpp
View file @ febc2a3a
...@@ -24,9 +24,9 @@ ...@@ -24,9 +24,9 @@
#include <iostream> #include <iostream>
#include "debug.h" #include "sims/nic/corundum/debug.h"
#include "mem.h" #include "sims/nic/corundum/mem.h"
#include "dma.h" #include "sims/nic/corundum/dma.h"
/* /*
* 1024 bits total data width * 1024 bits total data width
...@@ -85,7 +85,8 @@ void MemWriter::step() ...@@ -85,7 +85,8 @@ void MemWriter::step()
data_byte_width - data_offset : cur->len - cur_off); data_byte_width - data_offset : cur->len - cur_off);
for (size_t i = 0; i < cur_len; i++, off++) { for (size_t i = 0; i < cur_len; i++, off++) {
size_t byte_off = off % 4; size_t byte_off = off % 4;
p.mem_data[off / 4] |= (((uint32_t) cur->data[cur_off + i]) << (byte_off * 8)); p.mem_data[off / 4] |= (((uint32_t) cur->data[cur_off + i]) <<
(byte_off * 8));
p.mem_be[off / 32] |= (1 << (off % 32)); p.mem_be[off / 32] |= (1 << (off % 32));
p.mem_valid |= (1 << (off / (SEG_WIDTH / 8))); p.mem_valid |= (1 << (off / (SEG_WIDTH / 8)));
} }
...@@ -125,7 +126,8 @@ void MemReader::step() ...@@ -125,7 +126,8 @@ void MemReader::step()
if (cur && p.mem_resvalid && if (cur && p.mem_resvalid &&
((p.mem_resvalid & p.mem_valid) == p.mem_valid)) { ((p.mem_resvalid & p.mem_valid) == p.mem_valid)) {
#ifdef MEM_DEBUG #ifdef MEM_DEBUG
std::cerr << "completed read from: " << std::hex << cur->ram_addr << std::endl; std::cerr << "completed read from: " << std::hex << cur->ram_addr <<
std::endl;
std::cerr << " reval = " << (unsigned) p.mem_resvalid << std::endl; std::cerr << " reval = " << (unsigned) p.mem_resvalid << std::endl;
#endif #endif
p.mem_valid = 0; p.mem_valid = 0;
...@@ -139,7 +141,8 @@ void MemReader::step() ...@@ -139,7 +141,8 @@ void MemReader::step()
data_byte_width - off : cur->len - cur_off); data_byte_width - off : cur->len - cur_off);
for (size_t i = 0; i < cur_len; i++, off++) { for (size_t i = 0; i < cur_len; i++, off++) {
size_t byte_off = (off % 4); size_t byte_off = (off % 4);
cur->data[cur_off + i] = (p.mem_data[off / 4] >> (byte_off * 8)) & 0xff; cur->data[cur_off + i] = (p.mem_data[off / 4] >> (byte_off * 8)) &
0xff;
} }
cur_off += cur_len; cur_off += cur_len;
...@@ -158,7 +161,8 @@ void MemReader::step() ...@@ -158,7 +161,8 @@ void MemReader::step()
size_t data_offset = (cur->ram_addr + cur_off) % data_byte_width; size_t data_offset = (cur->ram_addr + cur_off) % data_byte_width;
#ifdef MEM_DEBUG #ifdef MEM_DEBUG
std::cerr << "issuing op=" << cur << " read from " << std::hex << cur->ram_addr << std::endl; std::cerr << "issuing op=" << cur << " read from " << std::hex <<
cur->ram_addr << std::endl;
std::cerr << " off=" << data_offset << std::endl; std::cerr << " off=" << data_offset << std::endl;
#endif #endif
...@@ -175,7 +179,7 @@ void MemReader::step() ...@@ -175,7 +179,7 @@ void MemReader::step()
for (size_t i = 0; i < cur_len; i++, off++) { for (size_t i = 0; i < cur_len; i++, off++) {
p.mem_valid |= (1 << (off / (SEG_WIDTH / 8))); p.mem_valid |= (1 << (off / (SEG_WIDTH / 8)));
} }
//p.mem_resready = p.mem_valid; // p.mem_resready = p.mem_valid;
p.mem_resready = 0xff; p.mem_resready = 0xff;
uint64_t seg_addr = (cur->ram_addr + cur_off) / data_byte_width; uint64_t seg_addr = (cur->ram_addr + cur_off) / data_byte_width;
...@@ -196,7 +200,6 @@ void MemReader::step() ...@@ -196,7 +200,6 @@ void MemReader::step()
std::cerr << " addr = " << p.mem_addr[i] << std::endl; std::cerr << " addr = " << p.mem_addr[i] << std::endl;
std::cerr << " mem_valid = " << (unsigned) p.mem_valid << std::endl; std::cerr << " mem_valid = " << (unsigned) p.mem_valid << std::endl;
#endif #endif
} }
} }
......
sims/nic/corundum/mem.h
View file @ febc2a3a
...@@ -22,13 +22,14 @@ ...@@ -22,13 +22,14 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ */
#ifndef DMA_H_ #ifndef MEM_H_
#define DMA_H_ #define MEM_H_
#include <deque> #include <deque>
#include "Vinterface.h" #include <verilated.h>
#include "verilated.h"
#include "sims/nic/corundum/obj_dir/Vinterface.h"
class DMAOp; class DMAOp;
...@@ -111,4 +112,4 @@ class MemWriter { ...@@ -111,4 +112,4 @@ class MemWriter {
void op_issue(DMAOp *op); void op_issue(DMAOp *op);
}; };
#endif /* ndef MEM_H_ */ #endif // MEM_H_
sims/nic/corundum/rules.mk
View file @ febc2a3a
...@@ -38,7 +38,7 @@ $(OBJS): CPPFLAGS := $(CPPFLAGS) -I$(d)include/ ...@@ -38,7 +38,7 @@ $(OBJS): CPPFLAGS := $(CPPFLAGS) -I$(d)include/
$(verilator_src_corundum): $(vsrcs_corundum) $(verilator_src_corundum): $(vsrcs_corundum)
$(VERILATOR) $(VFLAGS) --cc -O3 \ $(VERILATOR) $(VFLAGS) --cc -O3 \
-CFLAGS "-I$(abspath $(lib_dir)) -O3 -g -Wall -Wno-maybe-uninitialized" \ -CFLAGS "-I$(abspath $(lib_dir)) -iquote $(abspath $(base_dir)) -O3 -g -Wall -Wno-maybe-uninitialized" \
--Mdir $(verilator_dir_corundum) \ --Mdir $(verilator_dir_corundum) \
-y $(dir_corundum)rtl \ -y $(dir_corundum)rtl \
-y $(dir_corundum)lib/axi/rtl \ -y $(dir_corundum)lib/axi/rtl \
......
sims/nic/corundum_bm/corundum_bm.cc
View file @ febc2a3a
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include <signal.h> #include <signal.h>
#include <cassert> #include <cassert>
#include "corundum_bm.h" #include "sims/nic/corundum_bm/corundum_bm.h"
static nicbm::Runner *runner; static nicbm::Runner *runner;
...@@ -202,7 +202,8 @@ EventRing::issueEvent(unsigned type, unsigned source) ...@@ -202,7 +202,8 @@ EventRing::issueEvent(unsigned type, unsigned source)
fprintf(stderr, "Event ring is rull\n"); fprintf(stderr, "Event ring is rull\n");
return; return;
} }
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * EVENT_SIZE; addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) *
EVENT_SIZE;
/* Issue DMA write */ /* Issue DMA write */
DMAOp *op = new DMAOp; DMAOp *op = new DMAOp;
op->type = DMA_TYPE_EVENT; op->type = DMA_TYPE_EVENT;
...@@ -261,7 +262,8 @@ CplRing::complete(unsigned index, size_t len, bool tx) ...@@ -261,7 +262,8 @@ CplRing::complete(unsigned index, size_t len, bool tx)
this->pending.push_back(data); this->pending.push_back(data);
while (!full() && !this->pending.empty()) { while (!full() && !this->pending.empty()) {
CplData &data = this->pending.front(); CplData &data = this->pending.front();
addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) * CPL_SIZE; addr_t dma_addr = this->_dmaAddr + (this->_currHead & this->_sizeMask) *
CPL_SIZE;
/* Issue DMA write */ /* Issue DMA write */
DMAOp *op = new DMAOp; DMAOp *op = new DMAOp;
op->type = data.tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL; op->type = data.tx ? DMA_TYPE_TX_CPL : DMA_TYPE_RX_CPL;
...@@ -380,7 +382,8 @@ RxRing::rx(RxData *rx_data) ...@@ -380,7 +382,8 @@ RxRing::rx(RxData *rx_data)
delete rx_data; delete rx_data;
return; return;
} }
addr_t dma_addr = this->_dmaAddr + (this->_currTail & this->_sizeMask) * DESC_SIZE; addr_t dma_addr = this->_dmaAddr + (this->_currTail & this->_sizeMask) *
DESC_SIZE;
/* Issue DMA read */ /* Issue DMA read */
DMAOp *op = new DMAOp; DMAOp *op = new DMAOp;
op->type = DMA_TYPE_DESC; op->type = DMA_TYPE_DESC;
...@@ -804,7 +807,7 @@ Corundum::eth_rx(uint8_t port, const void *data, size_t len) ...@@ -804,7 +807,7 @@ Corundum::eth_rx(uint8_t port, const void *data, size_t len)
rxRing.rx(rx_data); rxRing.rx(rx_data);
} }
} //namespace corundum } // namespace corundum
using namespace corundum; using namespace corundum;
......
sims/nic/corundum_bm/corundum_bm.h
View file @ febc2a3a
...@@ -137,7 +137,7 @@ struct Desc { ...@@ -137,7 +137,7 @@ struct Desc {
uint16_t tx_csum_cmd; uint16_t tx_csum_cmd;
uint32_t len; uint32_t len;
uint64_t addr; uint64_t addr;
} __attribute__((packed)) ; } __attribute__((packed));
struct Cpl { struct Cpl {
uint16_t queue; uint16_t queue;
...@@ -154,7 +154,7 @@ struct Cpl { ...@@ -154,7 +154,7 @@ struct Cpl {
uint8_t rsvd3; uint8_t rsvd3;
uint32_t rsvd4; uint32_t rsvd4;
uint32_t rsvd5; uint32_t rsvd5;
} __attribute__((packed)) ; } __attribute__((packed));
#define EVENT_TYPE_TX_CPL 0x0000 #define EVENT_TYPE_TX_CPL 0x0000
#define EVENT_TYPE_RX_CPL 0x0001 #define EVENT_TYPE_RX_CPL 0x0001
...@@ -162,7 +162,7 @@ struct Cpl { ...@@ -162,7 +162,7 @@ struct Cpl {
struct Event { struct Event {
uint16_t type; uint16_t type;
uint16_t source; uint16_t source;
} __attribute__((packed)) ; } __attribute__((packed));
struct RxData { struct RxData {
size_t len; size_t len;
...@@ -231,7 +231,7 @@ public: ...@@ -231,7 +231,7 @@ public:
EventRing(); EventRing();
~EventRing(); ~EventRing();
virtual void dmaDone(DMAOp *op) override; void dmaDone(DMAOp *op) override;
void issueEvent(unsigned type, unsigned source); void issueEvent(unsigned type, unsigned source);
}; };
...@@ -240,7 +240,7 @@ public: ...@@ -240,7 +240,7 @@ public:
CplRing(EventRing *eventRing); CplRing(EventRing *eventRing);
~CplRing(); ~CplRing();
virtual void dmaDone(DMAOp *op) override; void dmaDone(DMAOp *op) override;
void complete(unsigned index, size_t len, bool tx); void complete(unsigned index, size_t len, bool tx);
private: private:
...@@ -258,8 +258,8 @@ public: ...@@ -258,8 +258,8 @@ public:
TxRing(CplRing *cplRing); TxRing(CplRing *cplRing);
~TxRing(); ~TxRing();
virtual void setHeadPtr(ptr_t ptr) override; void setHeadPtr(ptr_t ptr) override;
virtual void dmaDone(DMAOp *op) override; void dmaDone(DMAOp *op) override;
private: private:
CplRing *txCplRing; CplRing *txCplRing;
...@@ -270,7 +270,7 @@ public: ...@@ -270,7 +270,7 @@ public:
RxRing(CplRing *cplRing); RxRing(CplRing *cplRing);
~RxRing(); ~RxRing();
virtual void dmaDone(DMAOp *op) override; void dmaDone(DMAOp *op) override;
void rx(RxData *rx_data); void rx(RxData *rx_data);
private: private:
...@@ -338,4 +338,4 @@ private: ...@@ -338,4 +338,4 @@ private:
uint32_t features; uint32_t features;
}; };
} // namespace corundum } // namespace corundum
sims/nic/corundum_bm/tester.c
View file @ febc2a3a
...@@ -137,8 +137,8 @@ volatile union cosim_pcie_proto_d2h *d2h_poll() ...@@ -137,8 +137,8 @@ volatile union cosim_pcie_proto_d2h *d2h_poll()
void d2h_done(volatile union cosim_pcie_proto_d2h *msg) void d2h_done(volatile union cosim_pcie_proto_d2h *msg)
{ {
msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_MSG_MASK) | msg->dummy.own_type = (msg->dummy.own_type & COSIM_PCIE_PROTO_D2H_MSG_MASK)
COSIM_PCIE_PROTO_D2H_OWN_DEV; | COSIM_PCIE_PROTO_D2H_OWN_DEV;
d2h_pos = (d2h_pos + 1) % d2h_enum; d2h_pos = (d2h_pos + 1) % d2h_enum;
} }
...@@ -150,7 +150,8 @@ static void dev_read(uint64_t offset, uint16_t len) ...@@ -150,7 +150,8 @@ static void dev_read(uint64_t offset, uint16_t len)
read->offset = offset; read->offset = offset;
read->len = len; read->len = len;
read->bar = 0; read->bar = 0;
read->own_type = COSIM_PCIE_PROTO_H2D_MSG_READ | COSIM_PCIE_PROTO_H2D_OWN_DEV; read->own_type = COSIM_PCIE_PROTO_H2D_MSG_READ |
COSIM_PCIE_PROTO_H2D_OWN_DEV;
volatile union cosim_pcie_proto_d2h *d2h_msg = NULL; volatile union cosim_pcie_proto_d2h *d2h_msg = NULL;
while (d2h_msg == NULL) { while (d2h_msg == NULL) {
......
sims/nic/i40e_bm/headers.h
View file @ febc2a3a
...@@ -38,13 +38,13 @@ namespace headers { ...@@ -38,13 +38,13 @@ namespace headers {
struct eth_addr { struct eth_addr {
uint8_t addr[ETH_ADDR_LEN]; uint8_t addr[ETH_ADDR_LEN];
} __attribute__ ((packed)); } __attribute__((packed));
struct eth_hdr { struct eth_hdr {
struct eth_addr dest; struct eth_addr dest;
struct eth_addr src; struct eth_addr src;
uint16_t type; uint16_t type;
} __attribute__ ((packed)); } __attribute__((packed));
/******************************************************************************/ /******************************************************************************/
...@@ -68,7 +68,7 @@ struct eth_hdr { ...@@ -68,7 +68,7 @@ struct eth_hdr {
#define IP_PROTO_UDP 17 #define IP_PROTO_UDP 17
#define IP_PROTO_UDPLITE 136 #define IP_PROTO_UDPLITE 136
#define IP_PROTO_TCP 6 #define IP_PROTO_TCP 6
#define IP_PROTO_DCCP 33 #define IP_PROTO_DCCP 33
#define IP_ECN_NONE 0x0 #define IP_ECN_NONE 0x0
#define IP_ECN_ECT0 0x2 #define IP_ECN_ECT0 0x2
...@@ -95,7 +95,7 @@ struct ip_hdr { ...@@ -95,7 +95,7 @@ struct ip_hdr {
/* source and destination IP addresses */ /* source and destination IP addresses */
uint32_t src; uint32_t src;
uint32_t dest; uint32_t dest;
} __attribute__ ((packed)); } __attribute__((packed));
/******************************************************************************/ /******************************************************************************/
...@@ -140,14 +140,21 @@ struct arp_hdr { ...@@ -140,14 +140,21 @@ struct arp_hdr {
#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) #define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) #define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) #define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = \
#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS((uint16_t)(~(uint16_t)(TCP_FLAGS)))) | htons(flags)) htons(((len) << 12) | TCPH_FLAGS(phdr))
#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags)) #define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = \
(((phdr)->_hdrlen_rsvd_flags & PP_HTONS( \
(uint16_t)(~(uint16_t)(TCP_FLAGS)))) | htons(flags))
#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) \
(phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags))
#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags)) #define TCPH_SET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = \
#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) ((phdr)->_hdrlen_rsvd_flags | htons(flags))
#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = \
htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0)) #define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & \
(TCP_FIN | TCP_SYN)) != 0))
struct tcp_hdr { struct tcp_hdr {
uint16_t src; uint16_t src;
...@@ -178,23 +185,23 @@ struct udp_hdr { ...@@ -178,23 +185,23 @@ struct udp_hdr {
struct pkt_arp { struct pkt_arp {
struct eth_hdr eth; struct eth_hdr eth;
struct arp_hdr arp; struct arp_hdr arp;
} __attribute__ ((packed)); } __attribute__((packed));
struct pkt_ip { struct pkt_ip {
struct eth_hdr eth; struct eth_hdr eth;
struct ip_hdr ip; struct ip_hdr ip;
} __attribute__ ((packed)); } __attribute__((packed));
struct pkt_tcp { struct pkt_tcp {
struct eth_hdr eth; struct eth_hdr eth;
struct ip_hdr ip; struct ip_hdr ip;
struct tcp_hdr tcp; struct tcp_hdr tcp;
} __attribute__ ((packed)); } __attribute__((packed));
struct pkt_udp { struct pkt_udp {
struct eth_hdr eth; struct eth_hdr eth;
struct ip_hdr ip; struct ip_hdr ip;
struct udp_hdr udp; struct udp_hdr udp;
} __attribute__ ((packed)); } __attribute__((packed));
} // namespace headers } // namespace headers
sims/nic/i40e_bm/i40e_adminq.cc
View file @ febc2a3a
...@@ -27,9 +27,9 @@ ...@@ -27,9 +27,9 @@
#include <cassert> #include <cassert>
#include <iostream> #include <iostream>
#include "i40e_bm.h" #include "sims/nic/i40e_bm/i40e_bm.h"
#include "i40e_base_wrapper.h" #include "sims/nic/i40e_bm/i40e_base_wrapper.h"
using namespace i40e; using namespace i40e;
...@@ -188,8 +188,7 @@ void queue_admin_tx::admin_desc_ctx::process() ...@@ -188,8 +188,7 @@ void queue_admin_tx::admin_desc_ctx::process()
dev.regs.gllan_rctl_0 &= ~I40E_GLLAN_RCTL_0_PXE_MODE_MASK; dev.regs.gllan_rctl_0 &= ~I40E_GLLAN_RCTL_0_PXE_MODE_MASK;
desc_complete(0); desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_list_func_capabilities || } else if (d->opcode == i40e_aqc_opc_list_func_capabilities ||
d->opcode == i40e_aqc_opc_list_dev_capabilities) d->opcode == i40e_aqc_opc_list_dev_capabilities) {
{
#ifdef DEBUG_ADMINQ #ifdef DEBUG_ADMINQ
queue.log << " get dev/fun caps" << logger::endl; queue.log << " get dev/fun caps" << logger::endl;
#endif #endif
...@@ -270,16 +269,18 @@ void queue_admin_tx::admin_desc_ctx::process() ...@@ -270,16 +269,18 @@ void queue_admin_tx::admin_desc_ctx::process()
reinterpret_cast<struct i40e_aqc_get_link_status *>( reinterpret_cast<struct i40e_aqc_get_link_status *>(
d->params.raw); d->params.raw);
gls->command_flags &= I40E_AQ_LSE_IS_ENABLED; // should actually return gls->command_flags &= I40E_AQ_LSE_IS_ENABLED; // should actually return
// status of link status // status of link status
// notification // notification
gls->phy_type = I40E_PHY_TYPE_40GBASE_CR4_CU; gls->phy_type = I40E_PHY_TYPE_40GBASE_CR4_CU;
gls->link_speed = I40E_LINK_SPEED_40GB; gls->link_speed = I40E_LINK_SPEED_40GB;
gls->link_info = I40E_AQ_LINK_UP_FUNCTION | I40E_AQ_LINK_UP_PORT | gls->link_info = I40E_AQ_LINK_UP_FUNCTION | I40E_AQ_LINK_UP_PORT |
I40E_AQ_MEDIA_AVAILABLE | I40E_AQ_SIGNAL_DETECT; I40E_AQ_MEDIA_AVAILABLE | I40E_AQ_SIGNAL_DETECT;
gls->an_info = I40E_AQ_AN_COMPLETED | I40E_AQ_LP_AN_ABILITY; // might need qualified module // might need qualified module
gls->an_info = I40E_AQ_AN_COMPLETED | I40E_AQ_LP_AN_ABILITY;
gls->ext_info = 0; gls->ext_info = 0;
gls->loopback = I40E_AQ_LINK_POWER_CLASS_4 << I40E_AQ_PWR_CLASS_SHIFT_LB; gls->loopback = I40E_AQ_LINK_POWER_CLASS_4 <<
I40E_AQ_PWR_CLASS_SHIFT_LB;
gls->max_frame_size = dev.MAX_MTU; gls->max_frame_size = dev.MAX_MTU;
gls->config = I40E_AQ_CONFIG_CRC_ENA; gls->config = I40E_AQ_CONFIG_CRC_ENA;
...@@ -319,7 +320,7 @@ void queue_admin_tx::admin_desc_ctx::process() ...@@ -319,7 +320,7 @@ void queue_admin_tx::admin_desc_ctx::process()
// find start idx // find start idx
size_t cnt = sizeof(els) / sizeof(els[0]); size_t cnt = sizeof(els) / sizeof(els[0]);
size_t first = 0; size_t first = 0;
for (first = 0; first < cnt && els[first].seid < sw->seid; first++); for (first = 0; first < cnt && els[first].seid < sw->seid; first++) {}
// figure out how many fit in the buffer // figure out how many fit in the buffer
size_t max = (d->datalen - sizeof(hr)) / sizeof(els[0]); size_t max = (d->datalen - sizeof(hr)) / sizeof(els[0]);
...@@ -425,7 +426,7 @@ void queue_admin_tx::admin_desc_ctx::process() ...@@ -425,7 +426,7 @@ void queue_admin_tx::admin_desc_ctx::process()
#ifdef DEBUG_ADMINQ #ifdef DEBUG_ADMINQ
queue.log << " uknown opcode=" << d->opcode << logger::endl; queue.log << " uknown opcode=" << d->opcode << logger::endl;
#endif #endif
//desc_complete(I40E_AQ_RC_ESRCH); // desc_complete(I40E_AQ_RC_ESRCH);
desc_complete(0); desc_complete(0);
} }
} }
sims/nic/i40e_bm/i40e_base_wrapper.h
View file @ febc2a3a
...@@ -2,6 +2,9 @@ ...@@ -2,6 +2,9 @@
* Copyright(c) 2001-2020 Intel Corporation * Copyright(c) 2001-2020 Intel Corporation
*/ */
#ifndef I40E_BASE_WRAPPER_H_
#define I40E_BASE_WRAPPER_H_
#include <stdint.h> #include <stdint.h>
#define PF_DRIVER #define PF_DRIVER
...@@ -14,84 +17,84 @@ typedef uint16_t __le16; ...@@ -14,84 +17,84 @@ typedef uint16_t __le16;
typedef uint32_t __le32; typedef uint32_t __le32;
typedef uint64_t __le64; typedef uint64_t __le64;
#include "base/i40e_devids.h" #include "sims/nic/i40e_bm/base/i40e_devids.h"
#include "base/i40e_register.h" #include "sims/nic/i40e_bm/base/i40e_register.h"
#include "base/i40e_adminq_cmd.h" #include "sims/nic/i40e_bm/base/i40e_adminq_cmd.h"
#include "base/i40e_rxtxq.h" #include "sims/nic/i40e_bm/base/i40e_rxtxq.h"
/* from i40e_types.h */ /* from i40e_types.h */
/* Checksum and Shadow RAM pointers */ /* Checksum and Shadow RAM pointers */
#define I40E_SR_NVM_CONTROL_WORD 0x00 #define I40E_SR_NVM_CONTROL_WORD 0x00
#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
#define I40E_SR_OPTION_ROM_PTR 0x05 #define I40E_SR_OPTION_ROM_PTR 0x05
#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
#define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
#define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
#define I40E_SR_RO_PCIE_LCB_PTR 0x0A #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
#define I40E_SR_EMP_IMAGE_PTR 0x0B #define I40E_SR_EMP_IMAGE_PTR 0x0B
#define I40E_SR_PE_IMAGE_PTR 0x0C #define I40E_SR_PE_IMAGE_PTR 0x0C
#define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
#define I40E_SR_MNG_CONFIG_PTR 0x0E #define I40E_SR_MNG_CONFIG_PTR 0x0E
#define I40E_EMP_MODULE_PTR 0x0F #define I40E_EMP_MODULE_PTR 0x0F
#define I40E_SR_EMP_MODULE_PTR 0x48 #define I40E_SR_EMP_MODULE_PTR 0x48
#define I40E_SR_PBA_FLAGS 0x15 #define I40E_SR_PBA_FLAGS 0x15
#define I40E_SR_PBA_BLOCK_PTR 0x16 #define I40E_SR_PBA_BLOCK_PTR 0x16
#define I40E_SR_BOOT_CONFIG_PTR 0x17 #define I40E_SR_BOOT_CONFIG_PTR 0x17
#define I40E_NVM_OEM_VER_OFF 0x83 #define I40E_NVM_OEM_VER_OFF 0x83
#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
#define I40E_SR_NVM_WAKE_ON_LAN 0x19 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
#define I40E_SR_NVM_MAP_VERSION 0x29 #define I40E_SR_NVM_MAP_VERSION 0x29
#define I40E_SR_NVM_IMAGE_VERSION 0x2A #define I40E_SR_NVM_IMAGE_VERSION 0x2A
#define I40E_SR_NVM_STRUCTURE_VERSION 0x2B #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
#define I40E_SR_NVM_EETRACK_LO 0x2D #define I40E_SR_NVM_EETRACK_LO 0x2D
#define I40E_SR_NVM_EETRACK_HI 0x2E #define I40E_SR_NVM_EETRACK_HI 0x2E
#define I40E_SR_VPD_PTR 0x2F #define I40E_SR_VPD_PTR 0x2F
#define I40E_SR_PXE_SETUP_PTR 0x30 #define I40E_SR_PXE_SETUP_PTR 0x30
#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
#define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
#define I40E_SR_SW_CHECKSUM_WORD 0x3F #define I40E_SR_SW_CHECKSUM_WORD 0x3F
#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
#define I40E_PTR_TYPE BIT(15) #define I40E_PTR_TYPE BIT(15)
#define I40E_SR_OCP_CFG_WORD0 0x2B #define I40E_SR_OCP_CFG_WORD0 0x2B
#define I40E_SR_OCP_ENABLED BIT(15) #define I40E_SR_OCP_ENABLED BIT(15)
/* Shadow RAM related */ /* Shadow RAM related */
#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
#define I40E_SR_BUF_ALIGNMENT 4096 #define I40E_SR_BUF_ALIGNMENT 4096
#define I40E_SR_WORDS_IN_1KB 512 #define I40E_SR_WORDS_IN_1KB 512
/* Checksum should be calculated such that after adding all the words, /* Checksum should be calculated such that after adding all the words,
* including the checksum word itself, the sum should be 0xBABA. * including the checksum word itself, the sum should be 0xBABA.
*/ */
#define I40E_SR_SW_CHECKSUM_BASE 0xBABA #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
#define I40E_SRRD_SRCTL_ATTEMPTS 100000
#define I40E_SRRD_SRCTL_ATTEMPTS 100000
#endif // I40E_BASE_WRAPPER_H_
sims/nic/i40e_bm/i40e_bm.cc
View file @ febc2a3a
...@@ -27,9 +27,8 @@ ...@@ -27,9 +27,8 @@
#include <cassert> #include <cassert>
#include <iostream> #include <iostream>
#include "i40e_bm.h" #include "sims/nic/i40e_bm/i40e_bm.h"
#include "sims/nic/i40e_bm/i40e_base_wrapper.h"
#include "i40e_base_wrapper.h"
nicbm::Runner *runner; nicbm::Runner *runner;
...@@ -70,7 +69,6 @@ void i40e_bm::setup_intro(struct cosim_pcie_proto_dev_intro &di) ...@@ -70,7 +69,6 @@ void i40e_bm::setup_intro(struct cosim_pcie_proto_dev_intro &di)
di.pci_msix_table_offset = 0x0; di.pci_msix_table_offset = 0x0;
di.pci_msix_pba_offset = 0x1000; di.pci_msix_pba_offset = 0x1000;
di.psi_msix_cap_offset = 0x70; di.psi_msix_cap_offset = 0x70;
} }
void i40e_bm::dma_complete(nicbm::DMAOp &op) void i40e_bm::dma_complete(nicbm::DMAOp &op)
...@@ -163,88 +161,67 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -163,88 +161,67 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
uint32_t val = 0; uint32_t val = 0;
if (addr >= I40E_PFINT_DYN_CTLN(0) && if (addr >= I40E_PFINT_DYN_CTLN(0) &&
addr < I40E_PFINT_DYN_CTLN(NUM_PFINTS - 1)) addr < I40E_PFINT_DYN_CTLN(NUM_PFINTS - 1)) {
{
val = regs.pfint_dyn_ctln[(addr - I40E_PFINT_DYN_CTLN(0)) / 4]; val = regs.pfint_dyn_ctln[(addr - I40E_PFINT_DYN_CTLN(0)) / 4];
} else if (addr >= I40E_PFINT_LNKLSTN(0) && } else if (addr >= I40E_PFINT_LNKLSTN(0) &&
addr <= I40E_PFINT_LNKLSTN(NUM_PFINTS - 1)) addr <= I40E_PFINT_LNKLSTN(NUM_PFINTS - 1)) {
{
val = regs.pfint_lnklstn[(addr - I40E_PFINT_LNKLSTN(0)) / 4]; val = regs.pfint_lnklstn[(addr - I40E_PFINT_LNKLSTN(0)) / 4];
} else if (addr >= I40E_PFINT_RATEN(0) && } else if (addr >= I40E_PFINT_RATEN(0) &&
addr <= I40E_PFINT_RATEN(NUM_PFINTS - 1)) addr <= I40E_PFINT_RATEN(NUM_PFINTS - 1)) {
{
val = regs.pfint_raten[(addr - I40E_PFINT_RATEN(0)) / 4]; val = regs.pfint_raten[(addr - I40E_PFINT_RATEN(0)) / 4];
} else if (addr >= I40E_GLLAN_TXPRE_QDIS(0) && } else if (addr >= I40E_GLLAN_TXPRE_QDIS(0) &&
addr < I40E_GLLAN_TXPRE_QDIS(12)) addr < I40E_GLLAN_TXPRE_QDIS(12)) {
{
val = regs.gllan_txpre_qdis[(addr - I40E_GLLAN_TXPRE_QDIS(0)) / 4]; val = regs.gllan_txpre_qdis[(addr - I40E_GLLAN_TXPRE_QDIS(0)) / 4];
} else if (addr >= I40E_QINT_TQCTL(0) && } else if (addr >= I40E_QINT_TQCTL(0) &&
addr <= I40E_QINT_TQCTL(NUM_QUEUES - 1)) addr <= I40E_QINT_TQCTL(NUM_QUEUES - 1)) {
{
val = regs.qint_tqctl[(addr - I40E_QINT_TQCTL(0)) / 4]; val = regs.qint_tqctl[(addr - I40E_QINT_TQCTL(0)) / 4];
} else if (addr >= I40E_QTX_ENA(0) && } else if (addr >= I40E_QTX_ENA(0) &&
addr <= I40E_QTX_ENA(NUM_QUEUES - 1)) addr <= I40E_QTX_ENA(NUM_QUEUES - 1)) {
{
val = regs.qtx_ena[(addr - I40E_QTX_ENA(0)) / 4]; val = regs.qtx_ena[(addr - I40E_QTX_ENA(0)) / 4];
} else if (addr >= I40E_QTX_TAIL(0) && } else if (addr >= I40E_QTX_TAIL(0) &&
addr <= I40E_QTX_TAIL(NUM_QUEUES - 1)) addr <= I40E_QTX_TAIL(NUM_QUEUES - 1)) {
{
val = regs.qtx_tail[(addr - I40E_QTX_TAIL(0)) / 4]; val = regs.qtx_tail[(addr - I40E_QTX_TAIL(0)) / 4];
} else if (addr >= I40E_QTX_CTL(0) && } else if (addr >= I40E_QTX_CTL(0) &&
addr <= I40E_QTX_CTL(NUM_QUEUES - 1)) addr <= I40E_QTX_CTL(NUM_QUEUES - 1)) {
{
val = regs.qtx_ctl[(addr - I40E_QTX_CTL(0)) / 4]; val = regs.qtx_ctl[(addr - I40E_QTX_CTL(0)) / 4];
} else if (addr >= I40E_QINT_RQCTL(0) && } else if (addr >= I40E_QINT_RQCTL(0) &&
addr <= I40E_QINT_RQCTL(NUM_QUEUES - 1)) addr <= I40E_QINT_RQCTL(NUM_QUEUES - 1)) {
{
val = regs.qint_rqctl[(addr - I40E_QINT_RQCTL(0)) / 4]; val = regs.qint_rqctl[(addr - I40E_QINT_RQCTL(0)) / 4];
} else if (addr >= I40E_QRX_ENA(0) && } else if (addr >= I40E_QRX_ENA(0) &&
addr <= I40E_QRX_ENA(NUM_QUEUES - 1)) addr <= I40E_QRX_ENA(NUM_QUEUES - 1)) {
{
val = regs.qrx_ena[(addr - I40E_QRX_ENA(0)) / 4]; val = regs.qrx_ena[(addr - I40E_QRX_ENA(0)) / 4];
} else if (addr >= I40E_QRX_TAIL(0) && } else if (addr >= I40E_QRX_TAIL(0) &&
addr <= I40E_QRX_TAIL(NUM_QUEUES - 1)) addr <= I40E_QRX_TAIL(NUM_QUEUES - 1)) {
{
val = regs.qrx_tail[(addr - I40E_QRX_TAIL(0)) / 4]; val = regs.qrx_tail[(addr - I40E_QRX_TAIL(0)) / 4];
} else if (addr >= I40E_GLHMC_LANTXBASE(0) && } else if (addr >= I40E_GLHMC_LANTXBASE(0) &&
addr <= I40E_GLHMC_LANTXBASE(I40E_GLHMC_LANTXBASE_MAX_INDEX)) addr <= I40E_GLHMC_LANTXBASE(I40E_GLHMC_LANTXBASE_MAX_INDEX)) {
{
val = regs.glhmc_lantxbase[(addr - I40E_GLHMC_LANTXBASE(0)) / 4]; val = regs.glhmc_lantxbase[(addr - I40E_GLHMC_LANTXBASE(0)) / 4];
} else if (addr >= I40E_GLHMC_LANTXCNT(0) && } else if (addr >= I40E_GLHMC_LANTXCNT(0) &&
addr <= I40E_GLHMC_LANTXCNT(I40E_GLHMC_LANTXCNT_MAX_INDEX)) addr <= I40E_GLHMC_LANTXCNT(I40E_GLHMC_LANTXCNT_MAX_INDEX)) {
{
val = regs.glhmc_lantxcnt[(addr - I40E_GLHMC_LANTXCNT(0)) / 4]; val = regs.glhmc_lantxcnt[(addr - I40E_GLHMC_LANTXCNT(0)) / 4];
} else if (addr >= I40E_GLHMC_LANRXBASE(0) && } else if (addr >= I40E_GLHMC_LANRXBASE(0) &&
addr <= I40E_GLHMC_LANRXBASE(I40E_GLHMC_LANRXBASE_MAX_INDEX)) addr <= I40E_GLHMC_LANRXBASE(I40E_GLHMC_LANRXBASE_MAX_INDEX)) {
{
val = regs.glhmc_lanrxbase[(addr - I40E_GLHMC_LANRXBASE(0)) / 4]; val = regs.glhmc_lanrxbase[(addr - I40E_GLHMC_LANRXBASE(0)) / 4];
} else if (addr >= I40E_GLHMC_LANRXCNT(0) && } else if (addr >= I40E_GLHMC_LANRXCNT(0) &&
addr <= I40E_GLHMC_LANRXCNT(I40E_GLHMC_LANRXCNT_MAX_INDEX)) addr <= I40E_GLHMC_LANRXCNT(I40E_GLHMC_LANRXCNT_MAX_INDEX)) {
{
val = regs.glhmc_lanrxcnt[(addr - I40E_GLHMC_LANRXCNT(0)) / 4]; val = regs.glhmc_lanrxcnt[(addr - I40E_GLHMC_LANRXCNT(0)) / 4];
} else if (addr >= I40E_PFQF_HKEY(0) && } else if (addr >= I40E_PFQF_HKEY(0) &&
addr <= I40E_PFQF_HKEY(I40E_PFQF_HKEY_MAX_INDEX)) addr <= I40E_PFQF_HKEY(I40E_PFQF_HKEY_MAX_INDEX)) {
{
val = regs.pfqf_hkey[(addr - I40E_PFQF_HKEY(0)) / 128]; val = regs.pfqf_hkey[(addr - I40E_PFQF_HKEY(0)) / 128];
} else if (addr >= I40E_PFQF_HLUT(0) && } else if (addr >= I40E_PFQF_HLUT(0) &&
addr <= I40E_PFQF_HLUT(I40E_PFQF_HLUT_MAX_INDEX)) addr <= I40E_PFQF_HLUT(I40E_PFQF_HLUT_MAX_INDEX)) {
{
val = regs.pfqf_hlut[(addr - I40E_PFQF_HLUT(0)) / 128]; val = regs.pfqf_hlut[(addr - I40E_PFQF_HLUT(0)) / 128];
} else if (addr >= I40E_PFINT_ITRN(0, 0) && } else if (addr >= I40E_PFINT_ITRN(0, 0) &&
addr <= I40E_PFINT_ITRN(0, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(0, NUM_PFINTS - 1)) {
{
val = regs.pfint_itrn[0][(addr - I40E_PFINT_ITRN(0, 0)) / 4]; val = regs.pfint_itrn[0][(addr - I40E_PFINT_ITRN(0, 0)) / 4];
} else if (addr >= I40E_PFINT_ITRN(1, 0) && } else if (addr >= I40E_PFINT_ITRN(1, 0) &&
addr <= I40E_PFINT_ITRN(1, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(1, NUM_PFINTS - 1)) {
{
val = regs.pfint_itrn[1][(addr - I40E_PFINT_ITRN(1, 0)) / 4]; val = regs.pfint_itrn[1][(addr - I40E_PFINT_ITRN(1, 0)) / 4];
} else if (addr >= I40E_PFINT_ITRN(2, 0) && } else if (addr >= I40E_PFINT_ITRN(2, 0) &&
addr <= I40E_PFINT_ITRN(2, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(2, NUM_PFINTS - 1)) {
{
val = regs.pfint_itrn[2][(addr - I40E_PFINT_ITRN(2, 0)) / 4]; val = regs.pfint_itrn[2][(addr - I40E_PFINT_ITRN(2, 0)) / 4];
} else { } else {
switch (addr) { switch (addr) {
case I40E_PFGEN_CTRL: case I40E_PFGEN_CTRL:
val = 0; /* we always simulate immediate reset */ val = 0; /* we always simulate immediate reset */
...@@ -264,12 +241,12 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -264,12 +241,12 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
case I40E_GLNVM_GENS: case I40E_GLNVM_GENS:
val = I40E_GLNVM_GENS_NVM_PRES_MASK | val = I40E_GLNVM_GENS_NVM_PRES_MASK |
(6 << I40E_GLNVM_GENS_SR_SIZE_SHIFT); // shadow ram 64kb (6 << I40E_GLNVM_GENS_SR_SIZE_SHIFT); // shadow ram 64kb
break; break;
case I40E_GLNVM_FLA: case I40E_GLNVM_FLA:
val = I40E_GLNVM_FLA_LOCKED_MASK; /* normal flash programming val = I40E_GLNVM_FLA_LOCKED_MASK; // normal flash programming
mode */ // mode
break; break;
case I40E_GLGEN_RSTCTL: case I40E_GLGEN_RSTCTL:
...@@ -316,12 +293,9 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -316,12 +293,9 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
break; break;
case I40E_GLPCI_CNF2: case I40E_GLPCI_CNF2:
// that is ugly, but linux driver needs this not to crash
val = ((NUM_PFINTS - 2) << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) | val = ((NUM_PFINTS - 2) << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) |
(2 << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT); /* that is ugly, (2 << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT);
but linux
driver needs
this not to
crash. */
break; break;
case I40E_GLNVM_SRCTL: case I40E_GLNVM_SRCTL:
...@@ -338,7 +312,7 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -338,7 +312,7 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
break; break;
case I40E_PF_VT_PFALLOC: case I40E_PF_VT_PFALLOC:
val = 0; // we don't currently support VFs val = 0; // we don't currently support VFs
break; break;
case I40E_PFGEN_PORTNUM: case I40E_PFGEN_PORTNUM:
...@@ -351,14 +325,14 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -351,14 +325,14 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
case I40E_GLHMC_LANTXOBJSZ: case I40E_GLHMC_LANTXOBJSZ:
val = 7; // 128 B val = 7; // 128 B
break; break;
case I40E_GLHMC_LANQMAX: case I40E_GLHMC_LANQMAX:
val = NUM_QUEUES; val = NUM_QUEUES;
break; break;
case I40E_GLHMC_LANRXOBJSZ: case I40E_GLHMC_LANRXOBJSZ:
val = 5; // 32 B val = 5; // 32 B
break; break;
case I40E_GLHMC_FCOEMAX: case I40E_GLHMC_FCOEMAX:
...@@ -479,94 +453,73 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr) ...@@ -479,94 +453,73 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val) void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
{ {
if (addr >= I40E_PFINT_DYN_CTLN(0) && if (addr >= I40E_PFINT_DYN_CTLN(0) &&
addr <= I40E_PFINT_DYN_CTLN(NUM_PFINTS - 1)) addr <= I40E_PFINT_DYN_CTLN(NUM_PFINTS - 1)) {
{
regs.pfint_dyn_ctln[(addr - I40E_PFINT_DYN_CTLN(0)) / 4] = val; regs.pfint_dyn_ctln[(addr - I40E_PFINT_DYN_CTLN(0)) / 4] = val;
} else if (addr >= I40E_PFINT_LNKLSTN(0) && } else if (addr >= I40E_PFINT_LNKLSTN(0) &&
addr <= I40E_PFINT_LNKLSTN(NUM_PFINTS - 1)) addr <= I40E_PFINT_LNKLSTN(NUM_PFINTS - 1)) {
{
regs.pfint_lnklstn[(addr - I40E_PFINT_LNKLSTN(0)) / 4] = val; regs.pfint_lnklstn[(addr - I40E_PFINT_LNKLSTN(0)) / 4] = val;
} else if (addr >= I40E_PFINT_RATEN(0) && } else if (addr >= I40E_PFINT_RATEN(0) &&
addr <= I40E_PFINT_RATEN(NUM_PFINTS - 1)) addr <= I40E_PFINT_RATEN(NUM_PFINTS - 1)) {
{
regs.pfint_raten[(addr - I40E_PFINT_RATEN(0)) / 4] = val; regs.pfint_raten[(addr - I40E_PFINT_RATEN(0)) / 4] = val;
} else if (addr >= I40E_GLLAN_TXPRE_QDIS(0) && } else if (addr >= I40E_GLLAN_TXPRE_QDIS(0) &&
addr <= I40E_GLLAN_TXPRE_QDIS(11)) addr <= I40E_GLLAN_TXPRE_QDIS(11)) {
{
regs.gllan_txpre_qdis[(addr - I40E_GLLAN_TXPRE_QDIS(0)) / 4] = val; regs.gllan_txpre_qdis[(addr - I40E_GLLAN_TXPRE_QDIS(0)) / 4] = val;
} else if (addr >= I40E_QINT_TQCTL(0) && } else if (addr >= I40E_QINT_TQCTL(0) &&
addr <= I40E_QINT_TQCTL(NUM_QUEUES - 1)) addr <= I40E_QINT_TQCTL(NUM_QUEUES - 1)) {
{
regs.qint_tqctl[(addr - I40E_QINT_TQCTL(0)) / 4] = val; regs.qint_tqctl[(addr - I40E_QINT_TQCTL(0)) / 4] = val;
} else if (addr >= I40E_QTX_ENA(0) && } else if (addr >= I40E_QTX_ENA(0) &&
addr <= I40E_QTX_ENA(NUM_QUEUES - 1)) addr <= I40E_QTX_ENA(NUM_QUEUES - 1)) {
{
size_t idx = (addr - I40E_QTX_ENA(0)) / 4; size_t idx = (addr - I40E_QTX_ENA(0)) / 4;
regs.qtx_ena[idx] = val; regs.qtx_ena[idx] = val;
lanmgr.qena_updated(idx, false); lanmgr.qena_updated(idx, false);
} else if (addr >= I40E_QTX_TAIL(0) && } else if (addr >= I40E_QTX_TAIL(0) &&
addr <= I40E_QTX_TAIL(NUM_QUEUES - 1)) addr <= I40E_QTX_TAIL(NUM_QUEUES - 1)) {
{
size_t idx = (addr - I40E_QTX_TAIL(0)) / 4; size_t idx = (addr - I40E_QTX_TAIL(0)) / 4;
regs.qtx_tail[idx] = val; regs.qtx_tail[idx] = val;
lanmgr.tail_updated(idx, false); lanmgr.tail_updated(idx, false);
} else if (addr >= I40E_QTX_CTL(0) && } else if (addr >= I40E_QTX_CTL(0) &&
addr <= I40E_QTX_CTL(NUM_QUEUES - 1)) addr <= I40E_QTX_CTL(NUM_QUEUES - 1)) {
{
regs.qtx_ctl[(addr - I40E_QTX_CTL(0)) / 4] = val; regs.qtx_ctl[(addr - I40E_QTX_CTL(0)) / 4] = val;
} else if (addr >= I40E_QINT_RQCTL(0) && } else if (addr >= I40E_QINT_RQCTL(0) &&
addr <= I40E_QINT_RQCTL(NUM_QUEUES - 1)) addr <= I40E_QINT_RQCTL(NUM_QUEUES - 1)) {
{
regs.qint_rqctl[(addr - I40E_QINT_RQCTL(0)) / 4] = val; regs.qint_rqctl[(addr - I40E_QINT_RQCTL(0)) / 4] = val;
} else if (addr >= I40E_QRX_ENA(0) && } else if (addr >= I40E_QRX_ENA(0) &&
addr <= I40E_QRX_ENA(NUM_QUEUES - 1)) addr <= I40E_QRX_ENA(NUM_QUEUES - 1)) {
{
size_t idx = (addr - I40E_QRX_ENA(0)) / 4; size_t idx = (addr - I40E_QRX_ENA(0)) / 4;
regs.qrx_ena[idx] = val; regs.qrx_ena[idx] = val;
lanmgr.qena_updated(idx, true); lanmgr.qena_updated(idx, true);
} else if (addr >= I40E_QRX_TAIL(0) && } else if (addr >= I40E_QRX_TAIL(0) &&
addr <= I40E_QRX_TAIL(NUM_QUEUES - 1)) addr <= I40E_QRX_TAIL(NUM_QUEUES - 1)) {
{
size_t idx = (addr - I40E_QRX_TAIL(0)) / 4; size_t idx = (addr - I40E_QRX_TAIL(0)) / 4;
regs.qrx_tail[idx] = val; regs.qrx_tail[idx] = val;
lanmgr.tail_updated(idx, true); lanmgr.tail_updated(idx, true);
} else if (addr >= I40E_GLHMC_LANTXBASE(0) && } else if (addr >= I40E_GLHMC_LANTXBASE(0) &&
addr <= I40E_GLHMC_LANTXBASE(I40E_GLHMC_LANTXBASE_MAX_INDEX)) addr <= I40E_GLHMC_LANTXBASE(I40E_GLHMC_LANTXBASE_MAX_INDEX)) {
{
regs.glhmc_lantxbase[(addr - I40E_GLHMC_LANTXBASE(0)) / 4] = val; regs.glhmc_lantxbase[(addr - I40E_GLHMC_LANTXBASE(0)) / 4] = val;
} else if (addr >= I40E_GLHMC_LANTXCNT(0) && } else if (addr >= I40E_GLHMC_LANTXCNT(0) &&
addr <= I40E_GLHMC_LANTXCNT(I40E_GLHMC_LANTXCNT_MAX_INDEX)) addr <= I40E_GLHMC_LANTXCNT(I40E_GLHMC_LANTXCNT_MAX_INDEX)) {
{
regs.glhmc_lantxcnt[(addr - I40E_GLHMC_LANTXCNT(0)) / 4] = val; regs.glhmc_lantxcnt[(addr - I40E_GLHMC_LANTXCNT(0)) / 4] = val;
} else if (addr >= I40E_GLHMC_LANRXBASE(0) && } else if (addr >= I40E_GLHMC_LANRXBASE(0) &&
addr <= I40E_GLHMC_LANRXBASE(I40E_GLHMC_LANRXBASE_MAX_INDEX)) addr <= I40E_GLHMC_LANRXBASE(I40E_GLHMC_LANRXBASE_MAX_INDEX)) {
{
regs.glhmc_lanrxbase[(addr - I40E_GLHMC_LANRXBASE(0)) / 4] = val; regs.glhmc_lanrxbase[(addr - I40E_GLHMC_LANRXBASE(0)) / 4] = val;
} else if (addr >= I40E_GLHMC_LANRXCNT(0) && } else if (addr >= I40E_GLHMC_LANRXCNT(0) &&
addr <= I40E_GLHMC_LANRXCNT(I40E_GLHMC_LANRXCNT_MAX_INDEX)) addr <= I40E_GLHMC_LANRXCNT(I40E_GLHMC_LANRXCNT_MAX_INDEX)) {
{
regs.glhmc_lanrxcnt[(addr - I40E_GLHMC_LANRXCNT(0)) / 4] = val; regs.glhmc_lanrxcnt[(addr - I40E_GLHMC_LANRXCNT(0)) / 4] = val;
} else if (addr >= I40E_PFQF_HKEY(0) && } else if (addr >= I40E_PFQF_HKEY(0) &&
addr <= I40E_PFQF_HKEY(I40E_PFQF_HKEY_MAX_INDEX)) addr <= I40E_PFQF_HKEY(I40E_PFQF_HKEY_MAX_INDEX)) {
{
regs.pfqf_hkey[(addr - I40E_PFQF_HKEY(0)) / 128] = val; regs.pfqf_hkey[(addr - I40E_PFQF_HKEY(0)) / 128] = val;
lanmgr.rss_key_updated(); lanmgr.rss_key_updated();
} else if (addr >= I40E_PFQF_HLUT(0) && } else if (addr >= I40E_PFQF_HLUT(0) &&
addr <= I40E_PFQF_HLUT(I40E_PFQF_HLUT_MAX_INDEX)) addr <= I40E_PFQF_HLUT(I40E_PFQF_HLUT_MAX_INDEX)) {
{
regs.pfqf_hlut[(addr - I40E_PFQF_HLUT(0)) / 128] = val; regs.pfqf_hlut[(addr - I40E_PFQF_HLUT(0)) / 128] = val;
} else if (addr >= I40E_PFINT_ITRN(0, 0) && } else if (addr >= I40E_PFINT_ITRN(0, 0) &&
addr <= I40E_PFINT_ITRN(0, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(0, NUM_PFINTS - 1)) {
{
regs.pfint_itrn[0][(addr - I40E_PFINT_ITRN(0, 0)) / 4] = val; regs.pfint_itrn[0][(addr - I40E_PFINT_ITRN(0, 0)) / 4] = val;
} else if (addr >= I40E_PFINT_ITRN(1, 0) && } else if (addr >= I40E_PFINT_ITRN(1, 0) &&
addr <= I40E_PFINT_ITRN(1, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(1, NUM_PFINTS - 1)) {
{
regs.pfint_itrn[1][(addr - I40E_PFINT_ITRN(1, 0)) / 4] = val; regs.pfint_itrn[1][(addr - I40E_PFINT_ITRN(1, 0)) / 4] = val;
} else if (addr >= I40E_PFINT_ITRN(2, 0) && } else if (addr >= I40E_PFINT_ITRN(2, 0) &&
addr <= I40E_PFINT_ITRN(2, NUM_PFINTS - 1)) addr <= I40E_PFINT_ITRN(2, NUM_PFINTS - 1)) {
{
regs.pfint_itrn[2][(addr - I40E_PFINT_ITRN(2, 0)) / 4] = val; regs.pfint_itrn[2][(addr - I40E_PFINT_ITRN(2, 0)) / 4] = val;
} else { } else {
switch (addr) { switch (addr) {
...@@ -645,7 +598,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val) ...@@ -645,7 +598,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
pf_atq.reg_updated(); pf_atq.reg_updated();
break; break;
case I40E_PF_ATQBAH: case I40E_PF_ATQBAH:
regs.pf_atqba = ((uint64_t ) val << 32) | regs.pf_atqba = ((uint64_t) val << 32) |
(regs.pf_atqba & 0xffffffffULL); (regs.pf_atqba & 0xffffffffULL);
pf_atq.reg_updated(); pf_atq.reg_updated();
break; break;
...@@ -666,7 +619,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val) ...@@ -666,7 +619,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
regs.pf_arqba = val | (regs.pf_atqba & 0xffffffff00000000ULL); regs.pf_arqba = val | (regs.pf_atqba & 0xffffffff00000000ULL);
break; break;
case I40E_PF_ARQBAH: case I40E_PF_ARQBAH:
regs.pf_arqba = ((uint64_t ) val << 32) | regs.pf_arqba = ((uint64_t) val << 32) |
(regs.pf_arqba & 0xffffffffULL); (regs.pf_arqba & 0xffffffffULL);
break; break;
case I40E_PF_ARQLEN: case I40E_PF_ARQLEN:
...@@ -722,32 +675,32 @@ void i40e_bm::timed_event(nicbm::TimedEvent &ev) ...@@ -722,32 +675,32 @@ void i40e_bm::timed_event(nicbm::TimedEvent &ev)
{ {
int_ev &iev = *((int_ev *) &ev); int_ev &iev = *((int_ev *) &ev);
#ifdef DEBUG_DEV #ifdef DEBUG_DEV
log << "timed_event: triggering interrupt (" << iev.vector << ")" << log << "timed_event: triggering interrupt (" << iev.vec << ")" <<
logger::endl; logger::endl;
#endif #endif
iev.armed = false; iev.armed = false;
if (int_msix_en) { if (int_msix_en) {
runner->msix_issue(iev.vector); runner->msix_issue(iev.vec);
} else if (iev.vector > 0) { } else if (iev.vec > 0) {
log << "timed_event: MSI-X disabled, but vector != 0" << logger::endl; log << "timed_event: MSI-X disabled, but vec != 0" << logger::endl;
abort(); abort();
} else { } else {
runner->msi_issue(0); runner->msi_issue(0);
} }
} }
void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr) void i40e_bm::signal_interrupt(uint16_t vec, uint8_t itr)
{ {
int_ev &iev = intevs[vector]; int_ev &iev = intevs[vec];
uint64_t mindelay; uint64_t mindelay;
if (itr <= 2) { if (itr <= 2) {
// itr 0-2 // itr 0-2
if (vector == 0) if (vec == 0)
mindelay = regs.pfint_itr0[itr]; mindelay = regs.pfint_itr0[itr];
else else
mindelay = regs.pfint_itrn[itr][vector]; mindelay = regs.pfint_itrn[itr][vec];
mindelay *= 2000000ULL; mindelay *= 2000000ULL;
} else if (itr == 3) { } else if (itr == 3) {
// noitr // noitr
...@@ -762,7 +715,7 @@ void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr) ...@@ -762,7 +715,7 @@ void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr)
if (iev.armed && iev.time <= newtime) { if (iev.armed && iev.time <= newtime) {
// already armed and this is not scheduled sooner // already armed and this is not scheduled sooner
#ifdef DEBUG_DEV #ifdef DEBUG_DEV
log << "signal_interrupt: vector " << vector << " already scheduled" << log << "signal_interrupt: vec " << vec << " already scheduled" <<
logger::endl; logger::endl;
#endif #endif
return; return;
...@@ -775,7 +728,7 @@ void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr) ...@@ -775,7 +728,7 @@ void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr)
iev.time = newtime; iev.time = newtime;
#ifdef DEBUG_DEV #ifdef DEBUG_DEV
log << "signal_interrupt: scheduled vector " << vector << " for time=" << log << "signal_interrupt: scheduled vec " << vec << " for time=" <<
newtime << " (itr " << itr << ")" << logger::endl; newtime << " (itr " << itr << ")" << logger::endl;
#endif #endif
...@@ -797,7 +750,7 @@ void i40e_bm::reset(bool indicate_done) ...@@ -797,7 +750,7 @@ void i40e_bm::reset(bool indicate_done)
regs.glnvm_srctl = I40E_GLNVM_SRCTL_DONE_MASK; regs.glnvm_srctl = I40E_GLNVM_SRCTL_DONE_MASK;
for (uint16_t i = 0; i < NUM_PFINTS; i++) { for (uint16_t i = 0; i < NUM_PFINTS; i++) {
intevs[i].vector = i; intevs[i].vec = i;
if (intevs[i].armed) { if (intevs[i].armed) {
runner->event_cancel(intevs[i]); runner->event_cancel(intevs[i]);
intevs[i].armed = false; intevs[i].armed = false;
...@@ -904,7 +857,7 @@ int_ev::int_ev() ...@@ -904,7 +857,7 @@ int_ev::int_ev()
time = 0; time = 0;
} }
} //namespace i40e } // namespace i40e
using namespace i40e; using namespace i40e;
......
sims/nic/i40e_bm/i40e_bm.h
View file @ febc2a3a
...@@ -26,17 +26,18 @@ ...@@ -26,17 +26,18 @@
#include <deque> #include <deque>
#include <sstream> #include <sstream>
#include <string>
#include <stdint.h> #include <stdint.h>
extern "C" { extern "C" {
#include <simbricks/proto/pcie.h> #include <simbricks/proto/pcie.h>
} }
#include <simbricks/nicbm/nicbm.h> #include <simbricks/nicbm/nicbm.h>
//#define DEBUG_DEV // #define DEBUG_DEV
//#define DEBUG_ADMINQ // #define DEBUG_ADMINQ
//#define DEBUG_LAN // #define DEBUG_LAN
//#define DEBUG_HMC // #define DEBUG_HMC
//#define DEBUG_QUEUES // #define DEBUG_QUEUES
struct i40e_aq_desc; struct i40e_aq_desc;
struct i40e_tx_desc; struct i40e_tx_desc;
...@@ -54,7 +55,7 @@ class dma_base : public nicbm::DMAOp { ...@@ -54,7 +55,7 @@ class dma_base : public nicbm::DMAOp {
class int_ev : public nicbm::TimedEvent { class int_ev : public nicbm::TimedEvent {
public: public:
uint16_t vector; uint16_t vec;
bool armed; bool armed;
int_ev(); int_ev();
...@@ -124,6 +125,7 @@ class queue_base { ...@@ -124,6 +125,7 @@ class queue_base {
protected: protected:
queue_base &queue; queue_base &queue;
public: public:
enum state state; enum state state;
uint32_t index; uint32_t index;
...@@ -195,6 +197,7 @@ class queue_base { ...@@ -195,6 +197,7 @@ class queue_base {
public: public:
std::string qname; std::string qname;
logger log; logger log;
protected: protected:
desc_ctx *desc_ctxs[MAX_ACTIVE_DESCS]; desc_ctx *desc_ctxs[MAX_ACTIVE_DESCS];
uint32_t active_first_pos; uint32_t active_first_pos;
...@@ -233,6 +236,7 @@ class queue_base { ...@@ -233,6 +236,7 @@ class queue_base {
// called by dma op when writeback has completed // called by dma op when writeback has completed
void writeback_done(uint32_t first_pos, uint32_t cnt); void writeback_done(uint32_t first_pos, uint32_t cnt);
public: public:
queue_base(const std::string &qname_, uint32_t &reg_head_, queue_base(const std::string &qname_, uint32_t &reg_head_,
uint32_t &reg_tail_); uint32_t &reg_tail_);
...@@ -258,7 +262,7 @@ class queue_admin_tx : public queue_base { ...@@ -258,7 +262,7 @@ class queue_admin_tx : public queue_base {
// complete indirect response // complete indirect response
void desc_complete_indir(uint16_t retval, const void *data, void desc_complete_indir(uint16_t retval, const void *data,
size_t len, uint16_t extra_flags = 0, size_t len, uint16_t extra_flags = 0,
bool ignore_datalen=false); bool ignore_datalen = false);
public: public:
admin_desc_ctx(queue_admin_tx &queue_, i40e_bm &dev); admin_desc_ctx(queue_admin_tx &queue_, i40e_bm &dev);
...@@ -272,6 +276,7 @@ class queue_admin_tx : public queue_base { ...@@ -272,6 +276,7 @@ class queue_admin_tx : public queue_base {
uint32_t &reg_len; uint32_t &reg_len;
virtual desc_ctx &desc_ctx_create(); virtual desc_ctx &desc_ctx_create();
public: public:
queue_admin_tx(i40e_bm &dev_, uint64_t &reg_base_, queue_admin_tx(i40e_bm &dev_, uint64_t &reg_base_,
uint32_t &reg_len_, uint32_t &reg_head_, uint32_t &reg_tail_); uint32_t &reg_len_, uint32_t &reg_head_, uint32_t &reg_tail_);
...@@ -337,9 +342,9 @@ class lan_queue_base : public queue_base { ...@@ -337,9 +342,9 @@ class lan_queue_base : public queue_base {
uint32_t reg_dummy_head; uint32_t reg_dummy_head;
lan_queue_base(lan &lanmgr_, const std::string &qtype, uint32_t &reg_tail, lan_queue_base(lan &lanmgr_, const std::string &qtype,
size_t idx_, uint32_t &reg_tail, size_t idx_, uint32_t &reg_ena_,
uint32_t &reg_ena_, uint32_t &fpm_basereg, uint32_t &reg_intqctl, uint32_t &fpm_basereg, uint32_t &reg_intqctl,
uint16_t ctx_size); uint16_t ctx_size);
virtual void reset(); virtual void reset();
void enable(); void enable();
...@@ -435,7 +440,8 @@ class lan_queue_rx : public lan_queue_base { ...@@ -435,7 +440,8 @@ class lan_queue_rx : public lan_queue_base {
class rss_key_cache { class rss_key_cache {
protected: protected:
static const size_t key_len = 52; static const size_t key_len = 52;
static const size_t cache_len = 288; // big enough for 2x ipv6 (2x128 + 2x16) // big enough for 2x ipv6 (2x128 + 2x16)
static const size_t cache_len = 288;
bool cache_dirty; bool cache_dirty;
const uint32_t (&key)[key_len / 4]; const uint32_t (&key)[key_len / 4];
uint32_t cache[cache_len]; uint32_t cache[cache_len];
...@@ -622,4 +628,4 @@ void xsum_tcpip_tso(void *iphdr, uint8_t iplen, uint8_t l4len, ...@@ -622,4 +628,4 @@ void xsum_tcpip_tso(void *iphdr, uint8_t iplen, uint8_t l4len,
void tso_postupdate_header(void *iphdr, uint8_t iplen, uint8_t l4len, void tso_postupdate_header(void *iphdr, uint8_t iplen, uint8_t l4len,
uint16_t paylen); uint16_t paylen);
} // namespace corundum } // namespace i40e
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