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Commit f52b0898 authored by Antoine Kaufmann's avatar Antoine Kaufmann
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corundum checkpoint

parent e110ddd0
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Showing with 182 additions and 24 deletions
corundum/corundum_verilator.cpp
View file @ f52b0898
......@@ -11,11 +11,167 @@ double sc_time_stamp()
return main_time;
}
static void reset_inputs(Vinterface *top)
{
top->clk = 0;
top->rst = 0;
top->m_axis_ctrl_dma_read_desc_ready = 0;
top->s_axis_ctrl_dma_read_desc_status_tag = 0;
top->s_axis_ctrl_dma_read_desc_status_valid = 0;
top->m_axis_ctrl_dma_write_desc_ready = 0;
top->s_axis_ctrl_dma_write_desc_status_tag = 0;
top->s_axis_ctrl_dma_write_desc_status_valid = 0;
top->m_axis_data_dma_read_desc_ready = 0;
top->s_axis_data_dma_read_desc_status_tag = 0;
top->s_axis_data_dma_read_desc_status_valid = 0;
top->m_axis_data_dma_write_desc_ready = 0;
top->s_axis_data_dma_write_desc_status_tag = 0;
top->s_axis_data_dma_write_desc_status_valid = 0;
top->s_axil_awaddr = 0;
top->s_axil_awprot = 0;
top->s_axil_awvalid = 0;
top->s_axil_wdata = 0;
top->s_axil_wstrb = 0;
top->s_axil_wvalid = 0;
top->s_axil_bready = 0;
top->s_axil_araddr = 0;
top->s_axil_arprot = 0;
top->s_axil_arvalid = 0;
top->s_axil_rready = 0;
top->m_axil_csr_awready = 0;
top->m_axil_csr_wready = 0;
top->m_axil_csr_bresp = 0;
top->m_axil_csr_bvalid = 0;
top->m_axil_csr_arready = 0;
top->m_axil_csr_rdata = 0;
top->m_axil_csr_rresp = 0;
top->m_axil_csr_rvalid = 0;
top->ctrl_dma_ram_wr_cmd_sel = 0;
//top->ctrl_dma_ram_wr_cmd_be = 0;
//top->ctrl_dma_ram_wr_cmd_addr = 0;
top->ctrl_dma_ram_wr_cmd_valid = 0;
top->ctrl_dma_ram_rd_cmd_sel = 0;
//top->ctrl_dma_ram_rd_cmd_addr = 0;
top->ctrl_dma_ram_rd_cmd_valid = 0;
top->ctrl_dma_ram_rd_resp_ready = 0;
top->data_dma_ram_wr_cmd_sel = 0;
//top->data_dma_ram_wr_cmd_be = 0;
//top->data_dma_ram_wr_cmd_addr = 0;
top->data_dma_ram_wr_cmd_valid = 0;
top->data_dma_ram_rd_cmd_sel = 0;
//top->data_dma_ram_rd_cmd_addr = 0;
top->data_dma_ram_rd_cmd_valid = 0;
top->data_dma_ram_rd_resp_ready = 0;
top->tx_axis_tready = 0;
top->s_axis_tx_ptp_ts_valid = 0;
top->rx_axis_tkeep = 0;
top->rx_axis_tvalid = 0;
top->rx_axis_tlast = 0;
top->rx_axis_tuser = 0;
top->s_axis_rx_ptp_ts_valid = 0;
top->ptp_ts_step = 0;
}
static void report_output(const char *label, uint64_t val)
{
if (val == 0)
return;
std::cout << " " << label << " = " << val << std::endl;
}
static void report_outputs(Vinterface *top)
{
report_output("m_axis_ctrl_dma_read_desc_dma_addr", top->m_axis_ctrl_dma_read_desc_dma_addr);
report_output("m_axis_ctrl_dma_read_desc_ram_sel", top->m_axis_ctrl_dma_read_desc_ram_sel);
report_output("m_axis_ctrl_dma_read_desc_ram_addr", top->m_axis_ctrl_dma_read_desc_ram_addr);
report_output("m_axis_ctrl_dma_read_desc_len", top->m_axis_ctrl_dma_read_desc_len);
report_output("m_axis_ctrl_dma_read_desc_tag", top->m_axis_ctrl_dma_read_desc_tag);
report_output("m_axis_ctrl_dma_read_desc_valid", top->m_axis_ctrl_dma_read_desc_valid);
report_output("m_axis_ctrl_dma_write_desc_dma_addr", top->m_axis_ctrl_dma_write_desc_dma_addr);
report_output("m_axis_ctrl_dma_write_desc_ram_sel", top->m_axis_ctrl_dma_write_desc_ram_sel);
report_output("m_axis_ctrl_dma_write_desc_ram_addr", top->m_axis_ctrl_dma_write_desc_ram_addr);
report_output("m_axis_ctrl_dma_write_desc_len", top->m_axis_ctrl_dma_write_desc_len);
report_output("m_axis_ctrl_dma_write_desc_tag", top->m_axis_ctrl_dma_write_desc_tag);
report_output("m_axis_ctrl_dma_write_desc_valid", top->m_axis_ctrl_dma_write_desc_valid);
report_output("m_axis_data_dma_read_desc_dma_addr", top->m_axis_data_dma_read_desc_dma_addr);
report_output("m_axis_data_dma_read_desc_ram_sel", top->m_axis_data_dma_read_desc_ram_sel);
report_output("m_axis_data_dma_read_desc_ram_addr", top->m_axis_data_dma_read_desc_ram_addr);
report_output("m_axis_data_dma_read_desc_len", top->m_axis_data_dma_read_desc_len);
report_output("m_axis_data_dma_read_desc_tag", top->m_axis_data_dma_read_desc_tag);
report_output("m_axis_data_dma_read_desc_valid", top->m_axis_data_dma_read_desc_valid);
report_output("m_axis_data_dma_write_desc_dma_addr", top->m_axis_data_dma_write_desc_dma_addr);
report_output("m_axis_data_dma_write_desc_ram_sel", top->m_axis_data_dma_write_desc_ram_sel);
report_output("m_axis_data_dma_write_desc_ram_addr", top->m_axis_data_dma_write_desc_ram_addr);
report_output("m_axis_data_dma_write_desc_len", top->m_axis_data_dma_write_desc_len);
report_output("m_axis_data_dma_write_desc_tag", top->m_axis_data_dma_write_desc_tag);
report_output("m_axis_data_dma_write_desc_valid", top->m_axis_data_dma_write_desc_valid);
report_output("s_axil_awready", top->s_axil_awready);
report_output("s_axil_wready", top->s_axil_wready);
report_output("s_axil_bresp", top->s_axil_bresp);
report_output("s_axil_bvalid", top->s_axil_bvalid);
report_output("s_axil_arready", top->s_axil_arready);
report_output("s_axil_rdata", top->s_axil_rdata);
report_output("s_axil_rresp", top->s_axil_rresp);
report_output("s_axil_rvalid", top->s_axil_rvalid);
report_output("m_axil_csr_awaddr", top->m_axil_csr_awaddr);
report_output("m_axil_csr_awprot", top->m_axil_csr_awprot);
report_output("m_axil_csr_awvalid", top->m_axil_csr_awvalid);
report_output("m_axil_csr_wdata", top->m_axil_csr_wdata);
report_output("m_axil_csr_wstrb", top->m_axil_csr_wstrb);
report_output("m_axil_csr_wvalid", top->m_axil_csr_wvalid);
report_output("m_axil_csr_bready", top->m_axil_csr_bready);
report_output("m_axil_csr_araddr", top->m_axil_csr_araddr);
report_output("m_axil_csr_arprot", top->m_axil_csr_arprot);
report_output("m_axil_csr_arvalid", top->m_axil_csr_arvalid);
report_output("m_axil_csr_rready", top->m_axil_csr_rready);
report_output("ctrl_dma_ram_wr_cmd_ready", top->ctrl_dma_ram_wr_cmd_ready);
report_output("ctrl_dma_ram_rd_cmd_ready", top->ctrl_dma_ram_rd_cmd_ready);
report_output("ctrl_dma_ram_rd_resp_valid", top->ctrl_dma_ram_rd_resp_valid);
report_output("data_dma_ram_wr_cmd_ready", top->data_dma_ram_wr_cmd_ready);
report_output("data_dma_ram_rd_cmd_ready", top->data_dma_ram_rd_cmd_ready);
report_output("data_dma_ram_rd_resp_valid", top->data_dma_ram_rd_resp_valid);
report_output("tx_axis_tkeep", top->tx_axis_tkeep);
report_output("tx_axis_tvalid", top->tx_axis_tvalid);
report_output("tx_axis_tlast", top->tx_axis_tlast);
report_output("tx_axis_tuser", top->tx_axis_tuser);
report_output("s_axis_tx_ptp_ts_ready", top->s_axis_tx_ptp_ts_ready);
report_output("rx_axis_tready", top->rx_axis_tready);
report_output("s_axis_rx_ptp_ts_ready", top->s_axis_rx_ptp_ts_ready);
report_output("msi_irq", top->msi_irq);
}
int main(int argc, char *argv[])
{
Verilated::commandArgs(argc, argv);
Vinterface *top = new Vinterface;
// size: bar 0: 24 bits
reset_inputs(top);
top->rst = 1;
top->eval();
std::cout << "0 low:" << std::endl;
report_outputs(top);
top->clk = !top->clk;
top->eval();
std::cout << "0 high:" << std::endl;
report_outputs(top);
top->rst = 0;
top->clk = !top->clk;
top->eval();
std::cout << "1 low:" << std::endl;
report_outputs(top);
top->clk = !top->clk;
top->eval();
std::cout << "1 high:" << std::endl;
report_outputs(top);
top->final();
delete top;
return 0;
......
corundum/rtl/interface.v
View file @ f52b0898
......@@ -47,43 +47,43 @@ module interface #
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
parameter DMA_TAG_WIDTH = 8, /* this one is different */
// Number of outstanding operations (event queue)
parameter EVENT_QUEUE_OP_TABLE_SIZE = 16,
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
// Number of outstanding operations (transmit queue)
parameter TX_QUEUE_OP_TABLE_SIZE = 16,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
// Number of outstanding operations (receive queue)
parameter RX_QUEUE_OP_TABLE_SIZE = 16,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
// Number of outstanding operations (transmit completion queue)
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 16,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = 32,
// Number of outstanding operations (receive completion queue)
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 16,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = 32,
// Event queue index width
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter EVENT_QUEUE_INDEX_WIDTH = 5, /* this one is not explicitly set */
// Transmit queue index width
parameter TX_QUEUE_INDEX_WIDTH = 8,
parameter TX_QUEUE_INDEX_WIDTH = 13,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Transmit completion queue index width
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = 13,
// Receive completion queue index width
parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
// Pipeline setting (event queue)
parameter EVENT_QUEUE_PIPELINE = 3,
// Pipeline setting (transmit queue)
parameter TX_QUEUE_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 4,
// Pipeline setting (receive queue)
parameter RX_QUEUE_PIPELINE = 3,
// Pipeline setting (transmit completion queue)
parameter TX_CPL_QUEUE_PIPELINE = 3,
parameter TX_CPL_QUEUE_PIPELINE = 4,
// Pipeline setting (receive completion queue)
parameter RX_CPL_QUEUE_PIPELINE = 3,
// Transmit descriptor table size (number of in-flight operations)
parameter TX_DESC_TABLE_SIZE = 16,
parameter TX_DESC_TABLE_SIZE = 32,
// Transmit packet table size (number of in-progress packets)
parameter TX_PKT_TABLE_SIZE = 8,
// Receive descriptor table size (number of in-flight operations)
parameter RX_DESC_TABLE_SIZE = 16,
parameter RX_DESC_TABLE_SIZE = 32,
// Receive packet table size (number of in-progress packets)
parameter RX_PKT_TABLE_SIZE = 8,
// Transmit scheduler type
......@@ -91,9 +91,9 @@ module interface #
// Scheduler operation table size
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
// Scheduler pipeline setting
parameter TX_SCHEDULER_PIPELINE = 3,
parameter TX_SCHEDULER_PIPELINE = 4,
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
parameter TDMA_INDEX_WIDTH = 6,
// Interrupt number width
parameter INT_WIDTH = 8,
// Queue element pointer width
......@@ -101,7 +101,7 @@ module interface #
// Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
parameter LOG_BLOCK_SIZE_WIDTH = 2, /* this one is not explicitly set */
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
......@@ -117,25 +117,25 @@ module interface #
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 16,
parameter AXIL_ADDR_WIDTH = 24,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// DMA RAM segment count
parameter SEG_COUNT = 2,
parameter SEG_COUNT = (512 * 2 / 128),
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
parameter SEG_DATA_WIDTH = (512 * 2 / SEG_COUNT),
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
parameter SEG_ADDR_WIDTH = 12,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM segment select width
parameter RAM_SEL_WIDTH = $clog2(PORTS),
parameter RAM_SEL_WIDTH = 1,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
parameter AXIS_DATA_WIDTH = 64,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// Max transmit packet size
......
corundum/rtl/port.v
View file @ f52b0898
......@@ -607,7 +607,8 @@ always @(posedge clk) begin
axil_ctrl_wready_reg <= 1'b1;
axil_ctrl_bvalid_reg <= 1'b1;
case ({{(16 - AXIL_ADDR_WIDTH){1'b0}}, axil_ctrl_awaddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
//case ({{(16 - AXIL_ADDR_WIDTH){1'b0}}, axil_ctrl_awaddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
case ({axil_ctrl_awaddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
16'h0040: begin
// Scheduler enable
if (axil_ctrl_wstrb[0]) begin
......@@ -658,7 +659,8 @@ always @(posedge clk) begin
axil_ctrl_rvalid_reg <= 1'b1;
axil_ctrl_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}};
case ({{(16 - AXIL_ADDR_WIDTH){1'b0}}, axil_ctrl_araddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
//case ({{(16 - AXIL_ADDR_WIDTH){1'b0}}, axil_ctrl_araddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
case ({axil_ctrl_araddr[AXIL_ADDR_WIDTH - 1:2], 2'b00})
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // port_id
16'h0004: begin
// port_features
......
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