Merge branch 'master' of https://github.com/simbricks/simbricks

results/paper_data/sync-overhead/noTraf-gt-ib-sw-busy-1.json

+{"exp_name": "noTraf-gt-ib-sw-busy", "metadata": {}, "start_time": 1620378783.7463837, "end_time": 1620384847.4012096, "sims": {"nic.client.0.": {"class": "I40eNIC", "cmd": ["/home/hejingli/simbricks/sims/nic/i40e_bm/i40e_bm", "/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.pci.client.0.", "/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.eth.client.0.", "/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.shm.client.0.", "0", "0", "500", "500", "500"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received"], "stderr": ["7b294fabc00", "sync_pci=1 sync_eth=1", "exit main_time: 11191703619043"]}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/simbricks/sims/net/switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.eth.client.0."], "stdout": ["start polling"], "stderr": []}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/gem5-out.client.0", "/home/hejingli/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/0/gem5-cp.client.0", "--kernel=/home/hejingli/simbricks/images/vmlinux", "--disk-image=/home/hejingli/simbricks/images/output-base/base.raw", "--disk-image=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.pci.client.0.", "--simbricks-shm=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.shm.client.0.", "--simbricks-sync", "--simbricks-sync_mode=0", "--simbricks-pci-lat=500", "--simbricks-sync-int=500", "--simbricks-type=i40e"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  7 2021 04:15:50", "gem5 started May  7 2021 11:13:04", "gem5 executing on swsnetlab05, pid 59685", "command line: /home/hejingli/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/gem5-out.client.0 /home/hejingli/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/0/gem5-cp.client.0 --kernel=/home/hejingli/simbricks/images/vmlinux --disk-image=/home/hejingli/simbricks/images/output-base/base.raw --disk-image=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.pci.client.0. --simbricks-shm=/home/hejingli/simbricks/experiments/out/noTraf-gt-ib-sw-busy/1/nic.shm.client.0. --simbricks-sync --simbricks-sync_mode=0 --simbricks-pci-lat=500 --simbricks-sync-int=500 --simbricks-type=i40e", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1155191451544", "switching cpus", "**** REAL SIMULATION ****", "+ modprobe i40e\r", "[    0.753932] i40e: Intel(R) Ethernet Connection XL710 Network Driver - version 2.8.20-k\r", "[    0.753932] i40e: Copyright (c) 2013 - 2019 Intel Corporation.\r", "[    0.754932] i40e 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.754932] i40e 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.765930] i40e 0000:00:02.0: fw 0.0.00000 api 1.10 nvm 0.0.0 [8086:1572] [0000:0000]\r", "[    0.765930] i40e 0000:00:02.0: The driver for the device detected a newer version of the NVM image v1.10 than expected v1.9. Please install the most recent version of the network driver.\r", "[    0.886912] i40e 0000:00:02.0: This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\r", "[    0.888911] i40e 0000:00:02.0: Stopping firmware LLDP agent.\r", "[    0.889911] i40e 0000:00:02.0: MAC address: 00:bc:fa:94:b2:07\r", "[    0.889911] i40e 0000:00:02.0: FW LLDP is enabled\r", "[    0.894911] i40e 0000:00:02.0 eth0: NIC Link is Up, 40 Gbps Full Duplex, Flow Control: None\r", "[    0.975898] i40e 0000:00:02.0: PCI-Express: Speed UnknownGT/s Width xUnknown\r", "[    0.975898] i40e 0000:00:02.0: PCI-Express bandwidth available for this device may be insufficient for optimal performance.\r", "[    0.975898] i40e 0000:00:02.0: Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\r", "[    0.976898] i40e 0000:00:02.0: Features: PF-id[0] VSIs: 384 QP: 1 RSS VxLAN Geneve PTP VEPA\r", "+ ip link set dev eth0 up\r", "[    0.992896] i40e 0000:00:02.0: Error OK adding RX filters on PF, promiscuous mode forced on\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ dd if=/dev/urandom of=/dev/null count=500000\r", "[    1.001894] random: dd: uninitialized urandom read (512 bytes read)\r", "[    1.001894] random: dd: uninitialized urandom read (512 bytes read)\r", "[    1.001894] random: dd: uninitialized urandom read (512 bytes read)\r", "500000+0 records in\r", "500000+0 records out\r", "256000000 bytes (256 MB, 244 MiB) copied, 9.76752 s, 26209327 MB/s\r", "+ m5 exit\r", "Exiting @ tick 11191703384709 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1155191441544.  Starting simulation...", "info: Entering event queue @ 1155191451544.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1155191451867.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14", "warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!", "warn: instruction 'fdivrp' unimplemented", "warn: instruction 'fxam' unimplemented"]}}, "success": true}
\ No newline at end of file

results/paper_data/sync-overhead/no_simb-gt-busy-1.json

+{"exp_name": "no_simb-gt-busy", "metadata": {}, "start_time": 1620356029.1318808, "end_time": 1620362045.127793, "sims": {"host.host.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/1/gem5-out.host.0", "/home/hejingli/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/0/gem5-cp.host.0", "--kernel=/home/hejingli/simbricks/images/vmlinux", "--disk-image=/home/hejingli/simbricks/images/output-base/base.raw", "--disk-image=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/1/cfg.host.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "--no-simbricks", "-r", "0"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  7 2021 04:15:50", "gem5 started May  7 2021 04:53:49", "gem5 executing on swsnetlab05, pid 58453", "command line: /home/hejingli/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/1/gem5-out.host.0 /home/hejingli/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/0/gem5-cp.host.0 --kernel=/home/hejingli/simbricks/images/vmlinux --disk-image=/home/hejingli/simbricks/images/output-base/base.raw --disk-image=/home/hejingli/simbricks/experiments/out/no_simb-gt-busy/1/cfg.host.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 --no-simbricks -r 0", "", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1098650117143", "switching cpus", "**** REAL SIMULATION ****", "+ modprobe i40e\r", "[    0.731934] i40e: Intel(R) Ethernet Connection XL710 Network Driver - version 2.8.20-k\r", "[    0.731934] i40e: Copyright (c) 2013 - 2019 Intel Corporation.\r", "+ ip link set dev eth0 up\r", "Cannot find device \"eth0\"\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "Cannot find device \"eth0\"\r", "+ dd if=/dev/urandom of=/dev/null count=500000\r", "[    0.764929] random: dd: uninitialized urandom read (512 bytes read)\r", "[    0.764929] random: dd: uninitialized urandom read (512 bytes read)\r", "[    0.764929] random: dd: uninitialized urandom read (512 bytes read)\r", "500000+0 records in\r", "500000+0 records out\r", "256000000 bytes (256 MB, 244 MiB) copied, 9.75452 s, 26244252 MB/s\r", "+ m5 exit\r", "Exiting @ tick 10908369152892 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/simbricks/images/vmlinux", "system.pc.com_1.device: Listening for connections on port 3457", "0: system.remote_gdb: listening for remote gdb on port 7001", "warn: Reading current count from inactive timer.", "info: Entering event queue @ 1098650107143.  Starting simulation...", "info: Entering event queue @ 1098650117143.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1098650117466.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14", "warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!", "warn: instruction 'fdivrp' unimplemented", "warn: instruction 'fxam' unimplemented"]}}, "success": true}
\ No newline at end of file

results/sync-overhead.py

+# Copyright 2021 Max Planck Institute for Software Systems, and
+# National University of Singapore
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+import sys
+import os
+import pathlib
+import shutil
+import json
+
+# How to use
+# $ python3 modetcp.py paper_data/modetcp 
+#
+
+
+mode = ['no_simb-gt', 'noTraf-gt-ib-sw']
+cmd = ['sleep', 'busy']
+
+outdir = sys.argv[1]
+
+def parse_sim_time(path):
+    ret = {}
+    if not os.path.exists(path):
+        return ret
+    with open(path, 'r') as f:
+        data = json.load(f)
+
+    ret['simtime'] = (data['end_time'] - data['start_time'])/60
+    f.close()
+    return ret
+
+
+print('mode  sleep  busy')
+for m in mode:
+    line = m
+    for c in cmd:
+        path = '%s/%s-%s-1.json' % (outdir, m, c)
+        data = parse_sim_time(path)
+        if 'simtime' in data:
+            t = data['simtime']
+        else:
+            t = ''
+        line = line + ' ' + f'{t}'
+    print(line)
+
+