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ycai
simbricks
Commits
edc84de6
"...composable_kernel_rocm.git" did not exist on "f63a23acb14867da6f4a234aae19227a0847b4e6"
Commit
edc84de6
authored
May 04, 2023
by
Jonas Kaufmann
Committed by
Antoine Kaufmann
May 09, 2023
Browse files
sims/external/simics: add SimBricks PCIe adapter
parent
01bdcb45
Changes
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sims/external/simics/modules/simbricks-pcie/Makefile
sims/external/simics/modules/simbricks-pcie/Makefile
+28
-0
sims/external/simics/modules/simbricks-pcie/module_load.py
sims/external/simics/modules/simbricks-pcie/module_load.py
+41
-0
sims/external/simics/modules/simbricks-pcie/simbricks_pcie.c
sims/external/simics/modules/simbricks-pcie/simbricks_pcie.c
+1003
-0
sims/external/simics/modules/simbricks-pcie/simbricks_pcie_comp.py
...rnal/simics/modules/simbricks-pcie/simbricks_pcie_comp.py
+91
-0
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sims/external/simics/modules/simbricks-pcie/Makefile
0 → 100644
View file @
edc84de6
# -*- Makefile ; coding: utf-8 -*-
# © 2010 Intel Corporation
# Simics module makefile
MODULE_CLASSES
=
simbricks_pcie
MODULE_COMPONENTS
=
simbricks_pcie_comp
SRC_FILES
=
simbricks_pcie.c
PYTHON_FILES
=
simbricks_pcie_comp.py module_load.py
# SIMBRICKS_LIB needs to be set by caller
MODULE_CFLAGS
:=
-I
"
$(SIMBRICKS_LIB)
"
-Wno-address-of-packed-member
MODULE_LDFLAGS
:=
-L
"
$(SIMBRICKS_LIB)
"
-lsimbricks
D
:=
1
SIMICS_API
:=
6
THREAD_SAFE
:=
yes
COMPILE_PYC
=
0
ifeq
($(MODULE_MAKEFILE),)
$(error
Make
sure
you
compile
your
module
from
the
project
directory)
else
include
$(MODULE_MAKEFILE)
endif
sims/external/simics/modules/simbricks-pcie/module_load.py
0 → 100644
View file @
edc84de6
# SimBricks PCIe Adapter
#
# Copyright (c) 2020-2023 Max Planck Institute for Software Systems
# Copyright (c) 2020-2023 National University of Singapore
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
import
cli
class_name
=
'simbricks_pcie'
# info command prints static information
def
get_info
(
obj
):
return
[]
# status command prints dynamic information
def
get_status
(
obj
):
return
[(
'Registers'
,
[(
'Value'
,
obj
.
value
)])]
cli
.
new_info_command
(
class_name
,
get_info
)
cli
.
new_status_command
(
class_name
,
get_status
)
from
.
import
simbricks_pcie_comp
simbricks_pcie_comp
.
simbricks_pcie_comp
.
register
()
sims/external/simics/modules/simbricks-pcie/simbricks_pcie.c
0 → 100644
View file @
edc84de6
This diff is collapsed.
Click to expand it.
sims/external/simics/modules/simbricks-pcie/simbricks_pcie_comp.py
0 → 100644
View file @
edc84de6
# SimBricks PCIe Adapter Component
#
# Copyright (c) 2020-2023 Max Planck Institute for Software Systems
# Copyright (c) 2020-2023 National University of Singapore
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
import
simics
from
comp
import
StandardComponent
,
SimpleConfigAttribute
,
Interface
class
simbricks_pcie_comp
(
StandardComponent
):
"""SimBricks PCIe adapter device."""
_class_desc
=
'SimBricks PCIe adapter device'
_help_categories
=
(
'PCI'
,)
def
setup
(
self
):
super
().
setup
()
if
not
self
.
instantiated
.
val
:
self
.
add_objects
()
self
.
add_connectors
()
def
add_objects
(
self
):
simbricks_pcie_dev
=
self
.
add_pre_obj
(
'simbricks_pcie_dev'
,
'simbricks_pcie'
)
simbricks_pcie_dev
.
socket
=
self
.
socket
.
val
simbricks_pcie_dev
.
pci_latency
=
self
.
pci_latency
.
val
simbricks_pcie_dev
.
sync_period
=
self
.
sync_period
.
val
def
add_connectors
(
self
):
self
.
add_connector
(
slot
=
'pci_bus'
,
type
=
'pci-bus'
,
hotpluggable
=
True
,
required
=
True
,
multi
=
False
,
direction
=
simics
.
Sim_Connector_Direction_Up
)
class
basename
(
StandardComponent
.
basename
):
"""The default name for the created component."""
val
=
'simbricks_pcie'
class
socket
(
SimpleConfigAttribute
(
None
,
's'
,
simics
.
Sim_Attr_Required
)):
"""Socket Path for SimBricks messages."""
class
pci_latency
(
SimpleConfigAttribute
(
None
,
'i'
,
simics
.
Sim_Attr_Required
)
):
"""PCI Latency in nanoseconds from host to device."""
class
sync_period
(
SimpleConfigAttribute
(
None
,
'i'
,
simics
.
Sim_Attr_Required
)
):
"""Period for sending SimBricks synchronization messages in
nanoseconds."""
class
component_connector
(
Interface
):
"""Uses connector for handling connections between components."""
def
get_check_data
(
self
,
cnt
):
return
[]
def
get_connect_data
(
self
,
cnt
):
return
[[[
0
,
self
.
_up
.
get_slot
(
'simbricks_pcie_dev'
)]]]
def
check
(
self
,
cnt
,
attr
):
return
True
def
connect
(
self
,
cnt
,
attr
):
self
.
_up
.
get_slot
(
'simbricks_pcie_dev'
).
pci_bus
=
attr
[
1
]
def
disconnect
(
self
,
cnt
):
self
.
_up
.
get_slot
(
'simbricks_pcie_dev'
).
pci_bus
=
None
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