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ycai
simbricks
Commits
d62a440c
Unverified
Commit
d62a440c
authored
Jan 20, 2025
by
Jakob Görgen
Browse files
symphony/orchestration: increased default amount of memory for full system host
parent
2f2e030d
Changes
1
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1 changed file
with
3 additions
and
2 deletions
+3
-2
symphony/orchestration/simbricks/orchestration/system/host/base.py
...orchestration/simbricks/orchestration/system/host/base.py
+3
-2
No files found.
symphony/orchestration/simbricks/orchestration/system/host/base.py
View file @
d62a440c
...
@@ -70,16 +70,17 @@ class Host(base.Component):
...
@@ -70,16 +70,17 @@ class Host(base.Component):
return
instance
return
instance
def
connect_pcie_dev
(
self
,
dev
:
pcie
.
PCIeSimpleDevice
):
def
connect_pcie_dev
(
self
,
dev
:
pcie
.
PCIeSimpleDevice
)
->
pcie
.
PCIeChannel
:
pcie_if
=
pcie
.
PCIeHostInterface
(
self
)
pcie_if
=
pcie
.
PCIeHostInterface
(
self
)
self
.
add_if
(
pcie_if
)
self
.
add_if
(
pcie_if
)
pcichannel0
=
pcie
.
PCIeChannel
(
pcie_if
,
dev
.
_pci_if
)
pcichannel0
=
pcie
.
PCIeChannel
(
pcie_if
,
dev
.
_pci_if
)
return
pcichannel0
class
FullSystemHost
(
Host
):
class
FullSystemHost
(
Host
):
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
def
__init__
(
self
,
s
:
base
.
System
)
->
None
:
super
().
__init__
(
s
)
super
().
__init__
(
s
)
self
.
memory
:
int
=
512
self
.
memory
:
int
=
2048
self
.
cores
:
int
=
1
self
.
cores
:
int
=
1
self
.
cpu_freq
:
str
=
"3GHz"
self
.
cpu_freq
:
str
=
"3GHz"
self
.
disks
:
list
[
disk_images
.
DiskImage
]
=
[]
self
.
disks
:
list
[
disk_images
.
DiskImage
]
=
[]
...
...
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