experiments: add memory device support

Includes a new simulator type, and integration for host simulators to add
memory devices. Currently only implemented for gem5.

experiments/simbricks/orchestration/experiment/experiment_environment.py

@@ -62,6 +62,9 @@ class ExpEnv(object):
     def dev_pci_path(self, sim):
         return f'{self.workdir}/dev.pci.{sim.name}'
 
+    def dev_mem_path(self, sim):
+        return f'{self.workdir}/dev.mem.{sim.name}'
+
     def nic_eth_path(self, sim):
         return f'{self.workdir}/nic.eth.{sim.name}'
 

experiments/simbricks/orchestration/experiments.py

@@ -25,7 +25,7 @@ import typing as tp
 
 from simbricks.orchestration.proxy import NetProxyConnecter, NetProxyListener
 from simbricks.orchestration.simulators import (
-    HostSim, I40eMultiNIC, NetSim, NICSim, PCIDevSim, Simulator
+    HostSim, I40eMultiNIC, NetSim, NICSim, PCIDevSim, MemDevSim, Simulator
 )
 
 
@@ -55,6 +55,8 @@ class Experiment(object):
         """The host simulators to run."""
         self.pcidevs: tp.List[PCIDevSim] = []
         """The PCIe device simulators to run."""
+        self.memdevs: tp.List[MemDevSim] = []
+        """The memory device simulators to run."""
         self.networks: tp.List[NetSim] = []
         """The network simulators to run."""
         self.metadata = {}
@@ -78,6 +80,12 @@ class Experiment(object):
                 raise Exception('Duplicate pcidev name')
         self.pcidevs.append(sim)
 
+    def add_memdev(self, sim: MemDevSim):
+        for d in self.memdevs:
+            if d.name == sim.name:
+                raise Exception('Duplicate memdev name')
+        self.memdevs.append(sim)
+
     def add_network(self, sim: NetSim):
         for n in self.networks:
             if n.name == sim.name:
@@ -86,7 +94,8 @@ class Experiment(object):
 
     def all_simulators(self):
         """All simulators used in experiment."""
-        return itertools.chain(self.hosts, self.pcidevs, self.networks)
+        return itertools.chain(self.hosts, self.pcidevs, self.memdevs,
+                self.networks)
 
     def resreq_mem(self):
         """Memory required to run all simulators used in this experiment."""

experiments/simbricks/orchestration/simulators.py

@@ -198,6 +198,30 @@ class NetSim(Simulator):
         return [s for (_, s) in self.listen_sockets(env)]
 
 
+class MemDevSim(Simulator):
+    """Base class for memory device simulators."""
+    def __init__(self):
+        super().__init__()
+
+        self.name = ''
+        self.sync_mode = 0
+        self.start_tick = 0
+        self.sync_period = 500
+        self.mem_latency = 500
+        self.addr = 0xe000000000000000
+        self.size = 1024 * 1024 * 1024 # 1GB
+        self.as_id = 0
+
+    def full_name(self):
+        return 'mem.' + self.name
+
+    def sockets_cleanup(self, env):
+        return [env.dev_mem_path(self), env.dev_shm_path(self)]
+
+    def sockets_wait(self, env):
+        return [env.dev_mem_path(self)]
+
+
 class HostSim(Simulator):
     """Base class for host simulators."""
 
@@ -217,9 +241,11 @@ class HostSim(Simulator):
         self.sync_mode = 0
         self.sync_period = 500
         self.pci_latency = 500
+        self.mem_latency = 500
 
         self.pcidevs: tp.List[PCIDevSim] = []
         self.net_directs: tp.List[NetSim] = []
+        self.memdevs: tp.List[MemDevSim] = []
 
     @property
     def nics(self):
@@ -235,6 +261,10 @@ class HostSim(Simulator):
         dev.name = self.name + '.' + dev.name
         self.pcidevs.append(dev)
 
+    def add_memdev(self, dev: MemDevSim):
+        dev.name = self.name + '.' + dev.name
+        self.memdevs.append(dev)
+
     def add_netdirect(self, net: NetSim):
         net.hosts_direct.append(self)
         self.net_directs.append(net)
@@ -245,6 +275,8 @@ class HostSim(Simulator):
             deps.append(dev)
             if isinstance(dev, NICSim):
                 deps.append(dev.network)
+        for dev in self.memdevs:
+            deps.append(dev)
         return deps
 
     def wait_terminate(self):
@@ -315,6 +347,8 @@ class QemuHost(HostSim):
 
         # qemu does not currently support net direct ports
         assert len(self.net_directs) == 0
+        # qemu does not currently support mem device ports
+        assert len(self.memdevs) == 0
         return cmd
 
 
@@ -378,6 +412,17 @@ class Gem5Host(HostSim):
                 cmd += ':sync'
             cmd += ' '
 
+        for dev in self.memdevs:
+            cmd += (
+                f'--simbricks-mem={dev.size}@{dev.addr}@{dev.as_id}@'
+                f'connect:{env.dev_mem_path(dev)}'
+                f':latency={self.mem_latency}ns'
+                f':sync_interval={self.sync_period}ns'
+            )
+            if cpu_type == 'TimingSimpleCPU':
+                cmd += ':sync'
+            cmd += ' '
+
         for net in self.net_directs:
             cmd += (
                 '--simbricks-eth-e1000=listen'
@@ -620,3 +665,14 @@ class FEMUDev(PCIDevSim):
             f' {env.dev_pci_path(self)} {env.dev_shm_path(self)}'
         )
         return cmd
+
+
+class BasicMemDev(MemDevSim):
+    def run_cmd(self, env):
+        cmd = (
+            f'{env.repodir}/sims/mem/basicmem/basicmem'
+            f' {env.dev_mem_path(self)} {env.dev_shm_path(self)}'
+            f' {self.sync_mode} {self.start_tick} {self.sync_period}'
+            f' {self.mem_latency}'
+        )
+        return cmd