i40e: support for interrupt moderation

i40e_bm/i40e_bm.cc

@@ -574,6 +574,64 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
     }
 }
 
+void i40e_bm::timed_event(nicbm::TimedEvent &ev)
+{
+    int_ev &iev = *((int_ev *) &ev);
+#ifdef DEBUG_DEV
+    log << "timed_event: triggering interrupt (" << iev.vector << ")" <<
+        logger::endl;
+#endif
+    iev.armed = false;
+    runner->msi_issue(0);
+}
+
+void i40e_bm::signal_interrupt(uint16_t vector, uint8_t itr)
+{
+    if (vector != 0) {
+        log << "signal_interrupt() only supports vector 0" << logger::endl;
+        abort();
+    }
+
+    int_ev &iev = intevs[vector];
+
+    uint64_t mindelay;
+    if (itr <= 2) {
+        // itr 0-2
+        mindelay = regs.pfint_itr0[itr];
+        mindelay *= 2000000ULL;
+    } else if (itr == 3) {
+        // noitr
+        mindelay = 0;
+    } else {
+        log << "signal_interrupt() invalid itr (" << itr << ")" << logger::endl;
+        abort();
+    }
+
+    uint64_t curtime = runner->time_ps();
+    uint64_t newtime = curtime + mindelay;
+    if (iev.armed && iev.time <= newtime) {
+        // already armed and this is not scheduled sooner
+#ifdef DEBUG_DEV
+        log << "signal_interrupt: vector " << vector << " already scheduled" <<
+            logger::endl;
+#endif
+        return;
+    } else if (iev.armed) {
+        // need to reschedule
+        runner->event_cancel(iev);
+    }
+
+    iev.armed = true;
+    iev.time = newtime;
+
+#ifdef DEBUG_DEV
+    log << "signal_interrupt: scheduled vector " << vector << " for time=" <<
+        newtime << " (itr " << itr << ")" << logger::endl;
+#endif
+
+    runner->event_schedule(iev);
+}
+
 void i40e_bm::reset(bool indicate_done)
 {
 #ifdef DEBUG_DEV
@@ -587,6 +645,15 @@ void i40e_bm::reset(bool indicate_done)
     memset(&regs, 0, sizeof(regs));
     if (indicate_done)
         regs.glnvm_srctl = I40E_GLNVM_SRCTL_DONE_MASK;
+
+    for (uint16_t i = 0; i < NUM_PFINTS; i++) {
+        intevs[i].vector = i;
+        if (intevs[i].armed) {
+            runner->event_cancel(intevs[i]);
+            intevs[i].armed = false;
+        }
+        intevs[i].time = 0;
+    }
 }
 
 shadow_ram::shadow_ram(i40e_bm &dev_)
@@ -662,6 +729,12 @@ void shadow_ram::write(uint16_t addr, uint16_t val)
 #endif
 }
 
+int_ev::int_ev()
+{
+    armed = false;
+    time = 0;
+}
+
 } //namespace i40e
 
 using namespace i40e;

i40e_bm/i40e_bm.h

@@ -28,6 +28,15 @@ class dma_base : public nicbm::DMAOp {
         virtual void done() = 0;
 };
 
+class int_ev : public nicbm::TimedEvent {
+    public:
+        uint16_t vector;
+        bool armed;
+
+        int_ev();
+};
+
+
 class logger : public std::ostream {
     public:
         static const char endl = '\n';
@@ -496,8 +505,6 @@ protected:
     };
 
 public:
-    nicbm::Runner *runner;
-
     i40e_bm();
     ~i40e_bm();
 
@@ -509,6 +516,9 @@ public:
     virtual void reg_write32(uint8_t bar, uint64_t addr, uint32_t val);
     virtual void dma_complete(nicbm::DMAOp &op);
     virtual void eth_rx(uint8_t port, const void *data, size_t len);
+    virtual void timed_event(nicbm::TimedEvent &ev);
+
+    void signal_interrupt(uint16_t vector, uint8_t itr);
 
 protected:
     logger log;
@@ -518,6 +528,8 @@ protected:
     shadow_ram shram;
     lan lanmgr;
 
+    int_ev intevs[NUM_PFINTS];
+
     /** Read from the I/O bar */
     virtual uint32_t reg_io_read(uint64_t addr);
     /** Write to the I/O bar */

i40e_bm/i40e_lan.cc

@@ -171,7 +171,11 @@ void lan_queue_base::interrupt()
 #endif
     lanmgr.dev.regs.pfint_icr0 |= I40E_PFINT_ICR0_INTEVENT_MASK |
         (1 << (I40E_PFINT_ICR0_QUEUE_0_SHIFT + msix0_idx));
-    runner->msi_issue(0);
+
+    uint8_t itr = (qctl & I40E_QINT_TQCTL_ITR_INDX_MASK) >>
+        I40E_QINT_TQCTL_ITR_INDX_SHIFT;
+    lanmgr.dev.signal_interrupt(0, itr);
+
 }
 
 lan_queue_base::qctx_fetch::qctx_fetch(lan_queue_base &lq_)