Unverified Commit b5ef0c65 authored by Jakob Görgen's avatar Jakob Görgen
Browse files

updated all_simulators method in Simulation class + convenience function to...

updated all_simulators method in Simulation class + convenience function to get unique sync_period, eth_latency etc
parent 63c68148
...@@ -35,8 +35,3 @@ class Channel(sim_base.Simulator): ...@@ -35,8 +35,3 @@ class Channel(sim_base.Simulator):
def full_name(self) -> str: def full_name(self) -> str:
return "channel." + self.name return "channel." + self.name
# def add(self, ch: system_base.Channel):
# self.sys_channel = ch
# self.name = f"{ch.id}"
# self.experiment.sys_sim_map[ch] = self
...@@ -27,6 +27,7 @@ import typing as tp ...@@ -27,6 +27,7 @@ import typing as tp
import simbricks.orchestration.simulation.base as sim_base import simbricks.orchestration.simulation.base as sim_base
import simbricks.orchestration.system.pcie as system_pcie import simbricks.orchestration.system.pcie as system_pcie
import simbricks.orchestration.system as system import simbricks.orchestration.system as system
from simbricks.orchestration.instantiation import base as inst_base
from simbricks.orchestration.experiment.experiment_environment_new import ExpEnv from simbricks.orchestration.experiment.experiment_environment_new import ExpEnv
if tp.TYPE_CHECKING: if tp.TYPE_CHECKING:
...@@ -97,19 +98,15 @@ class Gem5Sim(HostSim): ...@@ -97,19 +98,15 @@ class Gem5Sim(HostSim):
def __init__(self, e: sim_base.Simulation): def __init__(self, e: sim_base.Simulation):
super().__init__(e) super().__init__(e)
self.name = '' self.name: str = ''
self.cpu_type_cp = 'X86KvmCPU' self.cpu_type_cp = 'X86KvmCPU'
self.cpu_type = 'TimingSimpleCPU' self.cpu_type = 'TimingSimpleCPU'
self.extra_main_args = [] self.extra_main_args: list[str] = []
self.extra_config_args = [] self.extra_config_args: list[str] = []
self.variant = 'fast' self.variant = 'fast'
self.modify_checkpoint_tick = True self.modify_checkpoint_tick = True
self.wait = True self.wait = True
def full_name(self) -> str:
return 'host.' + self.name
def resreq_cores(self) -> int: def resreq_cores(self) -> int:
return 1 return 1
...@@ -136,11 +133,12 @@ class Gem5Sim(HostSim): ...@@ -136,11 +133,12 @@ class Gem5Sim(HostSim):
return cmds return cmds
def run_cmd(self, env: ExpEnv) -> str: def run_cmd(self, inst: inst_base.Instantiation) -> str:
cpu_type = self.cpu_type cpu_type = self.cpu_type
if env.create_cp: if env.create_cp:
cpu_type = self.cpu_type_cp cpu_type = self.cpu_type_cp
# TODO
cmd = f'{env.gem5_path(self.variant)} --outdir={env.gem5_outdir(self)} ' cmd = f'{env.gem5_path(self.variant)} --outdir={env.gem5_outdir(self)} '
cmd += ' '.join(self.extra_main_args) cmd += ' '.join(self.extra_main_args)
cmd += ( cmd += (
...@@ -159,8 +157,8 @@ class Gem5Sim(HostSim): ...@@ -159,8 +157,8 @@ class Gem5Sim(HostSim):
) )
for dev in self.hosts[0].ifs: for dev in self.hosts[0].ifs: # TODO
if (dev == dev.channel.a): if (dev == dev.channel.a):
peer_if = dev.channel.b peer_if = dev.channel.b
else: else:
peer_if = dev.channel.a peer_if = dev.channel.a
...@@ -172,7 +170,7 @@ class Gem5Sim(HostSim): ...@@ -172,7 +170,7 @@ class Gem5Sim(HostSim):
f':latency={dev.channel.latency}ns' f':latency={dev.channel.latency}ns'
f':sync_interval={chn_sim.sync_period}ns' f':sync_interval={chn_sim.sync_period}ns'
) )
if cpu_type == 'TimingSimpleCPU': if cpu_type == 'TimingSimpleCPU' and: #TODO
cmd += ':sync' cmd += ':sync'
cmd += ' ' cmd += ' '
......
...@@ -74,33 +74,19 @@ class WireNet(NetSim): ...@@ -74,33 +74,19 @@ class WireNet(NetSim):
relative_executable_path="/sims/net/wire/net_wire", relative_executable_path="/sims/net/wire/net_wire",
relative_pcap_file_path=None, relative_pcap_file_path=None,
) )
# TODO: probably we want to store these in a common base class...
self._wire_comp: eth.EthWire | None = None self._wire_comp: eth.EthWire | None = None
self._relative_pcap_file_path: str | None = 'relative_pcap_file_path' self._relative_pcap_file_path: str | None = "relative_pcap_file_path"
def add(self, wire: eth.EthWire): def add(self, wire: eth.EthWire):
assert self._wire_comp is None assert self._wire_comp is None
super()._add_component(wire) super()._add_component(wire)
self.experiment.add_network(self)
self._wire_comp = wire self._wire_comp = wire
def run_cmd(self, inst: inst_base.Instantiation) -> str: def run_cmd(self, inst: inst_base.Instantiation) -> str:
eth_latency = None channels = self._get_channels(inst=inst)
sync_period = None eth_latency, sync_period, sync = (
run_sync = False sim_base.Simulator.get_unique_latency_period_sync(channels=channels)
channels = self._get_channels(inst=inst) )
for channel in channels:
sync_period = min(sync_period, channel.sync_period)
run_sync = run_sync or channel._synchronized
if (
channel.sys_channel.eth_latency != eth_latency
and eth_latency is not None
):
raise Exception("non unique eth latency")
eth_latency = channel.sys_channel.eth_latency
assert sync_period is not None
assert eth_latency is not None
sockets = self._get_sockets(inst=inst) sockets = self._get_sockets(inst=inst)
assert len(sockets) == 2 assert len(sockets) == 2
...@@ -127,35 +113,21 @@ class SwitchNet(NetSim): ...@@ -127,35 +113,21 @@ class SwitchNet(NetSim):
super().__init__( super().__init__(
simulation=simulation, relative_executable_path=relative_executable_path simulation=simulation, relative_executable_path=relative_executable_path
) )
# TODO: probably we want to store these in a common base class...
self._switch_spec: eth.EthSwitch | None = None self._switch_spec: eth.EthSwitch | None = None
self._relative_pcap_file_path: str | None = relative_pcap_file_path self._relative_pcap_file_path: str | None = relative_pcap_file_path
def add(self, switch_spec: eth.EthSwitch): def add(self, switch_spec: eth.EthSwitch):
assert self._switch_spec is None assert self._switch_spec is None
super()._add_component(switch_spec) super()._add_component(switch_spec)
self.experiment.add_network(self)
self._switch_spec = switch_spec self._switch_spec = switch_spec
def run_cmd(self, inst: inst_base.Instantiation) -> str: def run_cmd(self, inst: inst_base.Instantiation) -> str:
assert self._switch_spec is not None assert self._switch_spec is not None
eth_latency = None
sync_period = None
run_sync = False
channels = self._get_channels(inst=inst) channels = self._get_channels(inst=inst)
for channel in channels: eth_latency, sync_period, sync = (
sync_period = min(sync_period, channel.sync_period) sim_base.Simulator.get_unique_latency_period_sync(channels=channels)
run_sync = run_sync or channel._synchronized )
if (
channel.sys_channel.eth_latency != eth_latency
and eth_latency is not None
):
raise Exception("non unique eth latency")
eth_latency = channel.sys_channel.eth_latency
assert sync_period is not None
assert eth_latency is not None
cmd = inst.join_repo_base(self._relative_executable_path) cmd = inst.join_repo_base(self._relative_executable_path)
cmd += f" -S {sync_period} -E {eth_latency}" cmd += f" -S {sync_period} -E {eth_latency}"
......
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