i40e: more of an actual reset propagated through all components

i40e_bm/i40e_bm.cc

@@ -15,7 +15,7 @@ i40e_bm::i40e_bm()
     : pf_atq(*this, regs.pf_atqba, regs.pf_atqlen, regs.pf_atqh, regs.pf_atqt),
     hmc(*this), shram(*this), lanmgr(*this, NUM_QUEUES)
 {
-    memset(&regs, 0, sizeof(regs));
+    reset(false);
 }
 
 i40e_bm::~i40e_bm()
@@ -416,7 +416,7 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
             case I40E_PFGEN_CTRL:
                 if ((val & I40E_PFGEN_CTRL_PFSWR_MASK) ==
                         I40E_PFGEN_CTRL_PFSWR_MASK)
-                    reset();
+                    reset(true);
                 break;
 
             case I40E_GL_FWSTS:
@@ -515,11 +515,17 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
     }
 }
 
-void i40e_bm::reset()
+void i40e_bm::reset(bool indicate_done)
 {
     std::cout << "reset triggered" << std::endl;
 
-    regs.glnvm_srctl = I40E_GLNVM_SRCTL_DONE_MASK;
+    pf_atq.reset();
+    hmc.reset();
+    lanmgr.reset();
+
+    memset(&regs, 0, sizeof(regs));
+    if (indicate_done)
+        regs.glnvm_srctl = I40E_GLNVM_SRCTL_DONE_MASK;
 }
 
 shadow_ram::shadow_ram(i40e_bm &dev_)

i40e_bm/i40e_bm.h

@@ -96,6 +96,7 @@ class queue_base {
 
     public:
         queue_base(uint32_t &reg_head_, uint32_t &reg_tail_);
+        virtual void reset();
         void reg_updated();
         bool is_enabled();
 };
@@ -154,6 +155,7 @@ class host_mem_cache {
         };
 
         host_mem_cache(i40e_bm &dev);
+        void reset();
         void reg_updated(uint64_t addr);
 
         // issue a hmc memory operation (address is in the context
@@ -193,6 +195,7 @@ class lan_queue_base : public queue_base {
         lan_queue_base(lan &lanmgr_, uint32_t &reg_tail, size_t idx_,
                 uint32_t &reg_ena_, uint32_t &fpm_basereg, uint32_t &reg_intqctl,
                 uint16_t ctx_size);
+        virtual void reset();
         void enable();
         void disable();
 };
@@ -257,6 +260,7 @@ class lan_queue_rx : public lan_queue_base {
         lan_queue_rx(lan &lanmgr_, uint32_t &reg_tail, size_t idx,
                 uint32_t &reg_ena, uint32_t &fpm_basereg,
                 uint32_t &reg_intqctl);
+        virtual void reset();
         void packet_received(const void *data, size_t len);
 };
 
@@ -274,6 +278,7 @@ class lan {
 
     public:
         lan(i40e_bm &dev, size_t num_qs);
+        void reset();
         void qena_updated(uint16_t idx, bool rx);
         void tail_updated(uint16_t idx, bool rx);
         void packet_received(const void *data, size_t len);
@@ -384,7 +389,7 @@ protected:
     /** 32-bit write to the memory bar (should be the default) */
     virtual void reg_mem_write32(uint64_t addr, uint32_t val);
 
-    void reset();
+    void reset(bool indicate_done);
 };
 
 // places the tcp checksum in the packet (assuming ipv4)

i40e_bm/i40e_hmc.cc

@@ -13,6 +13,11 @@ extern nicbm::Runner *runner;
 
 host_mem_cache::host_mem_cache(i40e_bm &dev_)
     : dev(dev_)
+{
+    reset();
+}
+
+void host_mem_cache::reset()
 {
     for (size_t i = 0; i < MAX_SEGMENTS; i++) {
         segs[i].addr = 0;

i40e_bm/i40e_lan.cc

@@ -27,6 +27,14 @@ lan::lan(i40e_bm &dev_, size_t num_qs_)
     }
 }
 
+void lan::reset()
+{
+    for (size_t i = 0; i < num_qs; i++) {
+        rxqs[i]->reset();
+        txqs[i]->reset();
+    }
+}
+
 void lan::qena_updated(uint16_t idx, bool rx)
 {
     std::cerr << "lan: qena updated idx=" << idx << " rx=" << rx << std::endl;
@@ -70,6 +78,12 @@ lan_queue_base::lan_queue_base(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
     ctx = new uint8_t[ctx_size_];
 }
 
+void lan_queue_base::reset()
+{
+    enabling = false;
+    queue_base::reset();
+}
+
 void lan_queue_base::enable()
 {
     if (enabling || enabled)
@@ -157,6 +171,14 @@ lan_queue_rx::lan_queue_rx(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
 {
 }
 
+void lan_queue_rx::reset()
+{
+    dcache_first_idx = 0;
+    dcache_first_pos = 0;
+    dcache_first_cnt = 0;
+    queue_base::reset();
+}
+
 void lan_queue_rx::initialize()
 {
     std::cerr << "lan_queue_rx::initialize()" << std::endl;

i40e_bm/i40e_queues.cc

@@ -54,6 +54,12 @@ void queue_base::data_fetch(const void *desc, uint32_t idx, uint64_t addr,
     runner->issue_dma(*dma);
 }
 
+void queue_base::reset()
+{
+    enabled = false;
+    fetch_head = 0;
+}
+
 void queue_base::reg_updated()
 {
     if (!enabled)