sims/e1000_gem5: add event priorities for consistent ordering with timestamps

sims/nic/e1000_gem5/i8254xGBe.cc

@@ -62,12 +62,12 @@ IGbE::IGbE(const Params *p)
       fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
       rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
       pioDelay(p->pio_delay),
-      rdtrEvent([this]{ rdtrProcess(); }, "e1000-rdtr"),
-      radvEvent([this]{ radvProcess(); }, "e1000-radv"),
-      tadvEvent([this]{ tadvProcess(); }, "e1000-tadv"),
-      tidvEvent([this]{ tidvProcess(); }, "e1000-tidv"),
-      tickEvent([this]{ tick(); }, "e1000-tick"),
-      interEvent([this]{ delayIntEvent(); }, "e1000-inter"),
+      rdtrEvent([this]{ rdtrProcess(); }, "e1000-rdtr", false, 5),
+      radvEvent([this]{ radvProcess(); }, "e1000-radv", false, 6),
+      tadvEvent([this]{ tadvProcess(); }, "e1000-tadv", false,  7),
+      tidvEvent([this]{ tidvProcess(); }, "e1000-tidv", false, 8),
+      tickEvent([this]{ tick(); }, "e1000-tick", false,  9),
+      interEvent([this]{ delayIntEvent(); }, "e1000-inter", false, 12),
       rxDescCache(this, "RxDesc", p->rx_desc_cache_size),
       txDescCache(this, "TxDesc", p->tx_desc_cache_size),
       lastInterrupt(0)
@@ -765,10 +765,10 @@ template<class T>
 IGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s)
     : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0),
       wbOut(0), moreToWb(false), wbAlignment(0), pktPtr(NULL),
-      wbDelayEvent([this]{ writeback1(); }, n),
-      fetchDelayEvent([this]{ fetchDescriptors1(); }, n),
-      fetchEvent([this]{ fetchComplete(); }, n),
-      wbEvent([this]{ wbComplete(); }, n)
+      wbDelayEvent([this]{ writeback1(); }, n, false, 13),
+      fetchDelayEvent([this]{ fetchDescriptors1(); }, n, false, 14),
+      fetchEvent([this]{ fetchComplete(); }, n, false, 15),
+      wbEvent([this]{ wbComplete(); }, n, false, 16)
 {
     fetchBuf = new T[size];
     wbBuf = new T[size];
@@ -1056,9 +1056,9 @@ IGbE::DescCache<T>::reset()
 
 IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
     : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0),
-    pktEvent([this]{ pktComplete(); }, n),
-    pktHdrEvent([this]{ pktSplitDone(); }, n),
-    pktDataEvent([this]{ pktSplitDone(); }, n)
+    pktEvent([this]{ pktComplete(); }, n, false, 17),
+    pktHdrEvent([this]{ pktSplitDone(); }, n, false, 18),
+    pktDataEvent([this]{ pktSplitDone(); }, n, false, 19)
 
 {
     annSmFetch = "RX Desc Fetch";
@@ -1392,9 +1392,9 @@ IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
       useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0),
       tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false),
       tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0),
-    pktEvent([this]{ pktComplete(); }, n),
-    headerEvent([this]{ headerComplete(); }, n),
-    nullEvent([this]{ nullCallback(); }, n)
+    pktEvent([this]{ pktComplete(); }, n, false, 20),
+    headerEvent([this]{ headerComplete(); }, n, false, 21),
+    nullEvent([this]{ nullCallback(); }, n, false, 22)
 {
     annSmFetch = "TX Desc Fetch";
     annSmWb = "TX Desc Writeback";

sims/nic/e1000_gem5/support.h

@@ -42,9 +42,12 @@ class EventFunctionWrapper : public nicbm::TimedEvent {
     std::string _name;
 
     EventFunctionWrapper(const std::function<void(void)> &callback,
-                         const std::string &name)
+                         const std::string &name, bool free=false,
+                         int prio=0)
         : sched(false), callback(callback), _name(name)
-    { }
+    {
+      priority_ = prio;
+    }
 
     virtual ~EventFunctionWrapper() = default;
     bool scheduled() { return sched; }