add corundum and verilator build files

corundum/Makefile

+CXXFLAGS = -Wall
+
+VERILATOR = verilator
+VFLAGS = +1364-2005ext+v \
+    -Wno-WIDTH -Wno-PINMISSING -Wno-LITENDIAN -Wno-IMPLICIT -Wno-SELRANGE \
+    -Wno-CASEINCOMPLETE -Wno-UNSIGNED
+
+SRCS = corundum_verilator.cpp
+
+all: corundum_verilator
+
+obj_dir/Vinterface.cpp: rtl/interface.v
+	$(VERILATOR) $(VFLAGS) --cc \
+	    -y rtl \
+	    -y lib/axi/rtl \
+	    -y lib/eth/lib/axis/rtl/ \
+	    -y ./lib/pcie/rtl \
+	    rtl/interface.v --exe $(SRCS)
+
+obj_dir/Vinterface: obj_dir/Vinterface.cpp $(SRCS)
+	 $(MAKE) -C obj_dir -f Vinterface.mk
+
+corundum_verilator: obj_dir/Vinterface
+	cp $< $@
+
+#obj_dir/%.o: CXXFLAGS += -Wno-all
+#obj_dir/%.o: CPPFLAGS += -I /usr/share/verilator/include/
+#
+#obj_dir/verilated.o: /usr/share/verilator/include/verilated.cpp
+#	$(CXX) $(CXXFLAGS) -c $< -o $@
+#
+#obj_dir/verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp
+#	$(CXX) $(CXXFLAGS) -c $< -o $@
+#
+#corundum_verilator: corundum_verilator.o obj_dir/verilated.o \
+#	    obj_dir/verilated_vcd_c.o obj_dir/Vinterface.o \
+#	    obj_dir/Vinterface__Syms.o obj_dir/Vinterface__Trace.o \
+#	    obj_dir/Vinterface__Trace__Slow.o
+#	$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)
+
+clean:
+	rm -rf obj_dir corundum_verilator *.o
+
+.PHONY: all clean

corundum/README.md

+Commit `d0c9a83752cde7715787aa31a5bb951fc808e0cc` from https://github.com/ucsdsysnet/corundum.

corundum/corundum_verilator.cpp

+#include <iostream>
+
+#include "Vinterface.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+static uint64_t main_time = 0;
+
+double sc_time_stamp()
+{
+    return main_time;
+}
+
+int main(int argc, char *argv[])
+{
+    Verilated::commandArgs(argc, argv);
+    Vinterface *top = new Vinterface;
+
+    top->final();
+    delete top;
+    return 0;
+}

corundum/lib/axi/.gitignore

+*~
+*.lxt
+*.pyc
+*.vvp
+*.kate-swp
+

corundum/lib/axi/AUTHORS

+Alex Forencich <alex@alexforencich.com>

corundum/lib/axi/COPYING

+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

corundum/lib/axi/README

+README.md
\ No newline at end of file

corundum/lib/axi/README.md

+# Verilog AXI Components Readme
+
+For more information and updates: http://alexforencich.com/wiki/en/verilog/axi/start
+
+GitHub repository: https://github.com/alexforencich/verilog-axi
+
+## Introduction
+
+Collection of AXI4 and AXI4 lite bus components.  Most components are fully
+parametrizable in interface widths.  Includes full MyHDL testbench with
+intelligent bus cosimulation endpoints.
+
+## Documentation
+
+### axi_adapter module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.  Wrapper for axi_adapter_rd and axi_adapter_wr.
+
+### axi_adapter_rd module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.
+
+### axi_adapter_wr module
+
+AXI width adapter module with parametrizable data and address interface widths.
+Supports INCR burst types and narrow bursts.
+
+### axi_axil_adapter module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+Wrapper for axi_axil_adapter_rd and axi_axil_adapter_wr.
+
+### axi_axil_adapter_rd module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+
+### axi_axil_adapter_wr module
+
+AXI to AXI lite converter and width adapter module with parametrizable data
+and address interface widths.  Supports INCR burst types and narrow bursts.
+
+### axi_cdma module
+
+AXI to AXI DMA engine with parametrizable data and address interface widths.
+Generates full-width INCR bursts only, with parametrizable maximum burst
+length.  Supports unaligned transfers, which can be disabled via parameter
+to save on resource consumption.
+
+### axi_cdma_desc_mux module
+
+Descriptor multiplexer/demultiplexer for AXI CDMA module.  Enables sharing the
+AXI CDMA module between multiple request sources, interleaving requests and
+distributing responses.
+
+### axi_crossbar module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Supports all burst
+types.  Fully nonblocking with completely separate read and write paths; ID
+based transaction ordering protection logic; and per-port address decode,
+admission control, and decode error handling.  Wrapper for axi_crossbar_rd and
+axi_crossbar_wr.  
+
+### axi_crossbar_addr module
+
+Address decode and admission control module for AXI nonblocking crossbar interconnect.
+
+### axi_crossbar_rd module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Read interface only.
+Supports all burst types.  Fully nonblocking with completely separate read and
+write paths; ID based transaction ordering protection logic; and per-port
+address decode, admission control, and decode error handling.
+
+### axi_crossbar_wr module
+
+AXI nonblocking crossbar interconnect with parametrizable data and address
+interface widths and master and slave interface counts.  Write interface only.
+Supports all burst types.  Fully nonblocking with completely separate read and
+write paths; ID based transaction ordering protection logic; and per-port
+address decode, admission control, and decode error handling.
+
+### axi_dma module
+
+AXI to AXI stream DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.  Wrapper for axi_dma_rd and
+axi_dma_wr.
+
+### axi_dma_desc_mux module
+
+Descriptor multiplexer/demultiplexer for AXI DMA module.  Enables sharing the
+AXI DMA module between multiple request sources, interleaving requests and
+distributing responses.
+
+### axi_dma_rd module
+
+AXI to AXI stream DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.
+
+### axi_dma_wr module
+
+AXI stream to AXI DMA engine with parametrizable data and address interface
+widths.  Generates full-width INCR bursts only, with parametrizable maximum
+burst length.  Supports unaligned transfers, which can be disabled via
+parameter to save on resource consumption.
+
+### axi_fifo module
+
+AXI FIFO with parametrizable data and address interface widths.  Supports all
+burst types.  Optionally can delay the address channel until either the write
+data is completely shifted into the FIFO or the read data FIFO has enough
+capacity to fit the whole burst.  Wrapper for axi_fifo_rd and axi_fifo_wr.
+
+### axi_fifo_rd module
+
+AXI FIFO with parametrizable data and address interface widths.  AR and R
+channels only.  Supports all burst types.  Optionally can delay the address
+channel until either the read data FIFO is empty or has enough capacity to fit
+the whole burst.
+
+### axi_fifo_wr module
+
+AXI FIFO with parametrizable data and address interface widths.  WR, W, and B
+channels only.  Supports all burst types.  Optionally can delay the address
+channel until the write data is shifted completely into the write data FIFO,
+or the current burst completely fills the write data FIFO.
+
+### axi_interconnect module
+
+AXI shared interconnect with parametrizable data and address interface
+widths and master and slave interface counts.  Supports all burst types.
+Small in area, but does not support concurrent operations.
+
+### axi_ram module
+
+AXI RAM with parametrizable data and address interface widths. Supports FIXED
+and INCR burst types as well as narrow bursts.
+
+### axi_register module
+
+AXI register with parametrizable data and address interface widths.  Supports
+all burst types.  Inserts simple buffers or skid buffers into all channels.
+Channel register types can be individually changed or bypassed.  Wrapper for
+axi_register_rd and axi_register_wr.
+
+### axi_register_rd module
+
+AXI register with parametrizable data and address interface widths.  AR and R
+channels only.  Supports all burst types.  Inserts simple buffers or skid
+buffers into all channels.  Channel register types can be individually changed
+or bypassed.
+
+### axi_register_wr module
+
+AXI register with parametrizable data and address interface widths.  WR, W,
+and B channels only.  Supports all burst types.  Inserts simple buffers or
+skid buffers into all channels.  Channel register types can be individually
+changed or bypassed.
+
+### axil_adapter module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.  Wrapper for axi_adapter_rd and axi_adapter_wr.
+
+### axil_adapter_rd module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.
+
+### axil_adapter_wr module
+
+AXI lite width adapter module with parametrizable data and address interface
+widths.
+
+### axil_cdc module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.  Wrapper for axi_cdc_rd and axi_cdc_wr.
+
+### axil_cdc_rd module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.
+
+### axil_cdc_wr module
+
+AXI lite clock domain crossing module with parametrizable data and address
+interface widths.
+
+### axil_interconnect module
+
+AXI lite shared interconnect with parametrizable data and address interface
+widths and master and slave interface counts.  Small in area, but does not
+support concurrent operations.
+
+### axil_ram module
+
+AXI lite RAM with parametrizable data and address interface widths.
+
+### axil_register module
+
+AXI lite register with parametrizable data and address interface widths.
+Inserts skid buffers into all channels.  Channel registers can be individually
+bypassed.  Wrapper for axil_register_rd and axil_register_wr.
+
+### axil_register_rd module
+
+AXI lite register with parametrizable data and address interface widths.  AR
+and R channels only.  Inserts simple buffers into all channels.  Channel
+registers can be individually bypassed.
+
+### axil_register_wr module
+
+AXI lite register with parametrizable data and address interface widths.  WR,
+W, and B channels only.  Inserts simple buffers into all channels.  Channel
+registers can be individually bypassed.
+
+### Common signals
+
+    awid     : Write address ID
+    awaddr   : Write address
+    awlen    : Write burst length
+    awsize   : Write burst size
+    awburst  : Write burst type
+    awlock   : Write locking
+    awcache  : Write cache handling
+    awprot   : Write protection level
+    awqos    : Write QoS setting
+    awregion : Write region
+    awuser   : Write user sideband signal
+    awvalid  : Write address valid
+    awready  : Write address ready (from slave)
+    wdata    : Write data
+    wstrb    : Write data strobe (byte select)
+    wlast    : Write data last transfer in burst
+    wuser    : Write data user sideband signal
+    wvalid   : Write data valid
+    wready   : Write data ready (from slave)
+    bid      : Write response ID
+    bresp    : Write response
+    buser    : Write response user sideband signal
+    bvalid   : Write response valid
+    bready   : Write response ready (from master)
+    arid     : Read address ID
+    araddr   : Read address
+    arlen    : Read burst length
+    arsize   : Read burst size
+    arburst  : Read burst type
+    arlock   : Read locking
+    arcache  : Read cache handling
+    arprot   : Read protection level
+    arqos    : Read QoS setting
+    arregion : Read region
+    aruser   : Read user sideband signal
+    arvalid  : Read address valid
+    arready  : Read address ready (from slave)
+    rid      : Read data ID
+    rdata    : Read data
+    rresp    : Read response
+    rlast    : Read data last transfer in burst
+    ruser    : Read data user sideband signal
+    rvalid   : Read response valid
+    rready   : Read response ready (from master)
+
+### Common parameters
+
+    ADDR_WIDTH           : width of awaddr and araddr signals
+    DATA_WIDTH           : width of wdata and rdata signals
+    STRB_WIDTH           : width of wstrb signal
+    ID_WIDTH             : width of *id signals
+    AWUSER_ENABLE        : enable awuser signal
+    AWUSER_WIDTH         : width of awuser signal
+    WUSER_ENABLE         : enable wuser signal
+    WUSER_WIDTH          : width of wuser signal
+    BUSER_ENABLE         : enable buser signal
+    BUSER_WIDTH          : width of buser signal
+    ARUSER_ENABLE        : enable aruser signal
+    ARUSER_WIDTH         : width of aruser signal
+    RUSER_ENABLE         : enable ruser signal
+    RUSER_WIDTH          : width of ruser signal
+
+### Source Files
+
+    rtl/arbiter.v                   : Parametrizable arbiter
+    rtl/axi_adapter.v               : AXI lite width converter
+    rtl/axi_adapter_rd.v            : AXI lite width converter (read)
+    rtl/axi_adapter_wr.v            : AXI lite width converter (write)
+    rtl/axi_axil_adapter.v          : AXI to AXI lite converter
+    rtl/axi_axil_adapter_rd.v       : AXI to AXI lite converter (read)
+    rtl/axi_axil_adapter_wr.v       : AXI to AXI lite converter (write)
+    rtl/axi_cdma.v                  : AXI central DMA engine
+    rtl/axi_cdma_desc_mux.v         : AXI CDMA descriptor mux
+    rtl/axi_crossbar.v              : AXI nonblocking crossbar interconnect
+    rtl/axi_crossbar_addr.v         : AXI crossbar address module
+    rtl/axi_crossbar_rd.v           : AXI crossbar read module
+    rtl/axi_crossbar_wr.v           : AXI crossbar write module
+    rtl/axi_dma.v                   : AXI DMA engine
+    rtl/axi_dma_desc_mux.v          : AXI DMA descriptor mux
+    rtl/axi_dma_rd.v                : AXI DMA engine (read)
+    rtl/axi_dma_wr.v                : AXI DMA engine (write)
+    rtl/axi_fifo.v                  : AXI FIFO
+    rtl/axi_fifo_rd.v               : AXI FIFO (read)
+    rtl/axi_fifo_wr.v               : AXI FIFO (write)
+    rtl/axi_interconnect.v          : AXI shared interconnect
+    rtl/axi_ram.v                   : AXI RAM
+    rtl/axi_register.v              : AXI register
+    rtl/axi_register_rd.v           : AXI register (read)
+    rtl/axi_register_wr.v           : AXI register (write)
+    rtl/axil_adapter.v              : AXI lite width converter
+    rtl/axil_adapter_rd.v           : AXI lite width converter (read)
+    rtl/axil_adapter_wr.v           : AXI lite width converter (write)
+    rtl/axil_cdc.v                  : AXI lite CDC
+    rtl/axil_cdc_rd.v               : AXI lite CDC (read)
+    rtl/axil_cdc_wr.v               : AXI lite CDC (write)
+    rtl/axil_interconnect.v         : AXI lite shared interconnect
+    rtl/axil_ram.v                  : AXI lite RAM
+    rtl/axil_register.v             : AXI lite register
+    rtl/axil_register_rd.v          : AXI lite register (read)
+    rtl/axil_register_wr.v          : AXI lite register (write)
+    rtl/priority_encoder.v          : Parametrizable priority encoder
+
+### AXI4-Lite Interface Example
+
+Write
+
+                ___     ___     ___     ___     ___    
+    clk     ___/   \___/   \___/   \___/   \___/   \___
+                _______
+    awid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awaddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    awvalid ___/       \_______________________________
+            ___________         _______________________
+    awready            \_______/
+                _______________
+    wdata   XXXX_DATA__________XXXXXXXXXXXXXXXXXXXXXXXX
+                _______________
+    wstrb   XXXX_STRB__________XXXXXXXXXXXXXXXXXXXXXXXX
+                _______________
+    wvalid  ___/               \_______________________
+                        _______
+    wready  ___________/       \_______________________
+                                        _______
+    bid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX
+                                        _______
+    bresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX
+                                        _______
+    bvalid  ___________________________/       \_______
+            ___________________________________________
+    bready
+
+
+Read
+
+                ___     ___     ___     ___     ___    
+    clk     ___/   \___/   \___/   \___/   \___/   \___
+                _______
+    arid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    araddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+                _______
+    arvalid ___/       \_______________________________
+            ___________________________________________
+    arready
+                                        _______
+    rid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX
+                                        _______
+    rdata   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_DATA__XXXXXXXX
+                                        _______
+    rresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX
+                                        _______
+    rvalid  ___________________________/       \_______
+            ___________________________________________
+    rready
+
+
+## Testing
+
+Running the included testbenches requires MyHDL and Icarus Verilog.  Make sure
+that myhdl.vpi is installed properly for cosimulation to work correctly.  The
+testbenches can be run with a Python test runner like nose or py.test, or the
+individual test scripts can be run with python directly.
+
+### Testbench Files
+
+    tb/axi.py            : MyHDL AXI4 master and memory BFM
+    tb/axil.py           : MyHDL AXI4 lite master and memory BFM

corundum/lib/axi/rtl/arbiter.v

+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Arbiter module
+ */
+module arbiter #
+(
+    parameter PORTS = 4,
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter TYPE = "PRIORITY",
+    // block type: "NONE", "REQUEST", "ACKNOWLEDGE"
+    parameter BLOCK = "NONE",
+    // LSB priority: "LOW", "HIGH"
+    parameter LSB_PRIORITY = "LOW"
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,
+
+    output wire [PORTS-1:0]         grant,
+    output wire                     grant_valid,
+    output wire [$clog2(PORTS)-1:0] grant_encoded
+);
+
+reg [PORTS-1:0] grant_reg = 0, grant_next;
+reg grant_valid_reg = 0, grant_valid_next;
+reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
+
+assign grant_valid = grant_valid_reg;
+assign grant = grant_reg;
+assign grant_encoded = grant_encoded_reg;
+
+wire request_valid;
+wire [$clog2(PORTS)-1:0] request_index;
+wire [PORTS-1:0] request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_inst (
+    .input_unencoded(request),
+    .output_valid(request_valid),
+    .output_encoded(request_index),
+    .output_unencoded(request_mask)
+);
+
+reg [PORTS-1:0] mask_reg = 0, mask_next;
+
+wire masked_request_valid;
+wire [$clog2(PORTS)-1:0] masked_request_index;
+wire [PORTS-1:0] masked_request_mask;
+
+priority_encoder #(
+    .WIDTH(PORTS),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_masked (
+    .input_unencoded(request & mask_reg),
+    .output_valid(masked_request_valid),
+    .output_encoded(masked_request_index),
+    .output_unencoded(masked_request_mask)
+);
+
+always @* begin
+    grant_next = 0;
+    grant_valid_next = 0;
+    grant_encoded_next = 0;
+    mask_next = mask_reg;
+
+    if (BLOCK == "REQUEST" && grant_reg & request) begin
+        // granted request still asserted; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
+        // granted request not yet acknowledged; hold it
+        grant_valid_next = grant_valid_reg;
+        grant_next = grant_reg;
+        grant_encoded_next = grant_encoded_reg;
+    end else if (request_valid) begin
+        if (TYPE == "PRIORITY") begin
+            grant_valid_next = 1;
+            grant_next = request_mask;
+            grant_encoded_next = request_index;
+        end else if (TYPE == "ROUND_ROBIN") begin
+            if (masked_request_valid) begin
+                grant_valid_next = 1;
+                grant_next = masked_request_mask;
+                grant_encoded_next = masked_request_index;
+                if (LSB_PRIORITY == "LOW") begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
+                end else begin
+                    mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
+                end
+            end else begin
+                grant_valid_next = 1;
+                grant_next = request_mask;
+                grant_encoded_next = request_index;
+                if (LSB_PRIORITY == "LOW") begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
+                end else begin
+                    mask_next = {PORTS{1'b1}} << (request_index + 1);
+                end
+            end
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        grant_reg <= 0;
+        grant_valid_reg <= 0;
+        grant_encoded_reg <= 0;
+        mask_reg <= 0;
+    end else begin
+        grant_reg <= grant_next;
+        grant_valid_reg <= grant_valid_next;
+        grant_encoded_reg <= grant_encoded_next;
+        mask_reg <= mask_next;
+    end
+end
+
+endmodule

corundum/lib/axi/rtl/axi_adapter.v

+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 width adapter
+ */
+module axi_adapter #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) interface data bus in bits
+    parameter S_DATA_WIDTH = 32,
+    // Width of input (slave) interface wstrb (width of data bus in words)
+    parameter S_STRB_WIDTH = (S_DATA_WIDTH/8),
+    // Width of output (master) interface data bus in bits
+    parameter M_DATA_WIDTH = 32,
+    // Width of output (master) interface wstrb (width of data bus in words)
+    parameter M_STRB_WIDTH = (M_DATA_WIDTH/8),
+    // Width of ID signal
+    parameter ID_WIDTH = 8,
+    // Propagate awuser signal
+    parameter AWUSER_ENABLE = 0,
+    // Width of awuser signal
+    parameter AWUSER_WIDTH = 1,
+    // Propagate wuser signal
+    parameter WUSER_ENABLE = 0,
+    // Width of wuser signal
+    parameter WUSER_WIDTH = 1,
+    // Propagate buser signal
+    parameter BUSER_ENABLE = 0,
+    // Width of buser signal
+    parameter BUSER_WIDTH = 1,
+    // Propagate aruser signal
+    parameter ARUSER_ENABLE = 0,
+    // Width of aruser signal
+    parameter ARUSER_WIDTH = 1,
+    // Propagate ruser signal
+    parameter RUSER_ENABLE = 0,
+    // Width of ruser signal
+    parameter RUSER_WIDTH = 1,
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0,
+    // Forward ID through adapter
+    parameter FORWARD_ID = 0
+)
+(
+    input  wire                     clk,
+    input  wire                     rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [ID_WIDTH-1:0]      s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [7:0]               s_axi_awlen,
+    input  wire [2:0]               s_axi_awsize,
+    input  wire [1:0]               s_axi_awburst,
+    input  wire                     s_axi_awlock,
+    input  wire [3:0]               s_axi_awcache,
+    input  wire [2:0]               s_axi_awprot,
+    input  wire [3:0]               s_axi_awqos,
+    input  wire [3:0]               s_axi_awregion,
+    input  wire [AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire                     s_axi_awvalid,
+    output wire                     s_axi_awready,
+    input  wire [S_DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [S_STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                     s_axi_wlast,
+    input  wire [WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire                     s_axi_wvalid,
+    output wire                     s_axi_wready,
+    output wire [ID_WIDTH-1:0]      s_axi_bid,
+    output wire [1:0]               s_axi_bresp,
+    output wire [BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire                     s_axi_bvalid,
+    input  wire                     s_axi_bready,
+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [S_DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,
+
+    /*
+     * AXI master interface
+     */
+    output wire [ID_WIDTH-1:0]      m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [7:0]               m_axi_awlen,
+    output wire [2:0]               m_axi_awsize,
+    output wire [1:0]               m_axi_awburst,
+    output wire                     m_axi_awlock,
+    output wire [3:0]               m_axi_awcache,
+    output wire [2:0]               m_axi_awprot,
+    output wire [3:0]               m_axi_awqos,
+    output wire [3:0]               m_axi_awregion,
+    output wire [AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire                     m_axi_awvalid,
+    input  wire                     m_axi_awready,
+    output wire [M_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [M_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                     m_axi_wlast,
+    output wire [WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire                     m_axi_wvalid,
+    input  wire                     m_axi_wready,
+    input  wire [ID_WIDTH-1:0]      m_axi_bid,
+    input  wire [1:0]               m_axi_bresp,
+    input  wire [BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire                     m_axi_bvalid,
+    output wire                     m_axi_bready,
+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [M_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready
+);
+
+axi_adapter_wr #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .AWUSER_ENABLE(AWUSER_ENABLE),
+    .AWUSER_WIDTH(AWUSER_WIDTH),
+    .WUSER_ENABLE(WUSER_ENABLE),
+    .WUSER_WIDTH(WUSER_WIDTH),
+    .BUSER_ENABLE(BUSER_ENABLE),
+    .BUSER_WIDTH(BUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);
+
+axi_adapter_rd #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .S_DATA_WIDTH(S_DATA_WIDTH),
+    .S_STRB_WIDTH(S_STRB_WIDTH),
+    .M_DATA_WIDTH(M_DATA_WIDTH),
+    .M_STRB_WIDTH(M_STRB_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
+    .FORWARD_ID(FORWARD_ID)
+)
+axi_adapter_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI master interface
+     */
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);
+
+endmodule

corundum/lib/axi/rtl/axi_axil_adapter.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4 to AXI4-Lite adapter
+ */
+module axi_axil_adapter #
+(
+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of input (slave) AXI interface data bus in bits
+    parameter AXI_DATA_WIDTH = 32,
+    // Width of input (slave) AXI interface wstrb (width of data bus in words)
+    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
+    // Width of AXI ID signal
+    parameter AXI_ID_WIDTH = 8,
+    // Width of output (master) AXI lite interface data bus in bits
+    parameter AXIL_DATA_WIDTH = 32,
+    // Width of output (master) AXI lite interface wstrb (width of data bus in words)
+    parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
+    // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
+    parameter CONVERT_BURST = 1,
+    // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
+    parameter CONVERT_NARROW_BURST = 0
+)
+(
+    input  wire                        clk,
+    input  wire                        rst,
+
+    /*
+     * AXI slave interface
+     */
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_awaddr,
+    input  wire [7:0]                  s_axi_awlen,
+    input  wire [2:0]                  s_axi_awsize,
+    input  wire [1:0]                  s_axi_awburst,
+    input  wire                        s_axi_awlock,
+    input  wire [3:0]                  s_axi_awcache,
+    input  wire [2:0]                  s_axi_awprot,
+    input  wire                        s_axi_awvalid,
+    output wire                        s_axi_awready,
+    input  wire [AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+    input  wire [AXI_STRB_WIDTH-1:0]   s_axi_wstrb,
+    input  wire                        s_axi_wlast,
+    input  wire                        s_axi_wvalid,
+    output wire                        s_axi_wready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_bid,
+    output wire [1:0]                  s_axi_bresp,
+    output wire                        s_axi_bvalid,
+    input  wire                        s_axi_bready,
+    input  wire [AXI_ID_WIDTH-1:0]     s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]       s_axi_araddr,
+    input  wire [7:0]                  s_axi_arlen,
+    input  wire [2:0]                  s_axi_arsize,
+    input  wire [1:0]                  s_axi_arburst,
+    input  wire                        s_axi_arlock,
+    input  wire [3:0]                  s_axi_arcache,
+    input  wire [2:0]                  s_axi_arprot,
+    input  wire                        s_axi_arvalid,
+    output wire                        s_axi_arready,
+    output wire [AXI_ID_WIDTH-1:0]     s_axi_rid,
+    output wire [AXI_DATA_WIDTH-1:0]   s_axi_rdata,
+    output wire [1:0]                  s_axi_rresp,
+    output wire                        s_axi_rlast,
+    output wire                        s_axi_rvalid,
+    input  wire                        s_axi_rready,
+
+    /*
+     * AXI lite master interface
+     */
+    output wire [ADDR_WIDTH-1:0]       m_axil_awaddr,
+    output wire [2:0]                  m_axil_awprot,
+    output wire                        m_axil_awvalid,
+    input  wire                        m_axil_awready,
+    output wire [AXIL_DATA_WIDTH-1:0]  m_axil_wdata,
+    output wire [AXIL_STRB_WIDTH-1:0]  m_axil_wstrb,
+    output wire                        m_axil_wvalid,
+    input  wire                        m_axil_wready,
+    input  wire [1:0]                  m_axil_bresp,
+    input  wire                        m_axil_bvalid,
+    output wire                        m_axil_bready,
+    output wire [ADDR_WIDTH-1:0]       m_axil_araddr,
+    output wire [2:0]                  m_axil_arprot,
+    output wire                        m_axil_arvalid,
+    input  wire                        m_axil_arready,
+    input  wire [AXIL_DATA_WIDTH-1:0]  m_axil_rdata,
+    input  wire [1:0]                  m_axil_rresp,
+    input  wire                        m_axil_rvalid,
+    output wire                        m_axil_rready
+);
+
+
+axi_axil_adapter_wr #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
+)
+axi_axil_adapter_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_awaddr(m_axil_awaddr),
+    .m_axil_awprot(m_axil_awprot),
+    .m_axil_awvalid(m_axil_awvalid),
+    .m_axil_awready(m_axil_awready),
+    .m_axil_wdata(m_axil_wdata),
+    .m_axil_wstrb(m_axil_wstrb),
+    .m_axil_wvalid(m_axil_wvalid),
+    .m_axil_wready(m_axil_wready),
+    .m_axil_bresp(m_axil_bresp),
+    .m_axil_bvalid(m_axil_bvalid),
+    .m_axil_bready(m_axil_bready)
+);
+
+axi_axil_adapter_rd #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
+    .CONVERT_BURST(CONVERT_BURST),
+    .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
+)
+axi_axil_adapter_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interface
+     */
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_araddr(m_axil_araddr),
+    .m_axil_arprot(m_axil_arprot),
+    .m_axil_arvalid(m_axil_arvalid),
+    .m_axil_arready(m_axil_arready),
+    .m_axil_rdata(m_axil_rdata),
+    .m_axil_rresp(m_axil_rresp),
+    .m_axil_rvalid(m_axil_rvalid),
+    .m_axil_rready(m_axil_rready)
+);
+
+endmodule

corundum/lib/axi/rtl/axi_cdma_desc_mux.v

+/*
+
+Copyright (c) 2019 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI CDMA descriptor mux
+ */
+module axi_cdma_desc_mux #
+(
+    // Number of ports
+    parameter PORTS = 2,
+    // AXI address width
+    parameter AXI_ADDR_WIDTH = 16,
+    // Length field width
+    parameter LEN_WIDTH = 20,
+    // Input tag field width
+    parameter S_TAG_WIDTH = 8,
+    // Output tag field width (towards CDMA module)
+    // Additional bits required for response routing
+    parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),
+    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+    parameter ARB_TYPE = "PRIORITY",
+    // LSB priority: "LOW", "HIGH"
+    parameter LSB_PRIORITY = "HIGH"
+)
+(
+    input  wire                            clk,
+    input  wire                            rst,
+
+    /*
+     * Descriptor output (to AXI CDMA core)
+     */
+    output wire [AXI_ADDR_WIDTH-1:0]       m_axis_desc_read_addr,
+    output wire [AXI_ADDR_WIDTH-1:0]       m_axis_desc_write_addr,
+    output wire [LEN_WIDTH-1:0]            m_axis_desc_len,
+    output wire [M_TAG_WIDTH-1:0]          m_axis_desc_tag,
+    output wire                            m_axis_desc_valid,
+    input  wire                            m_axis_desc_ready,
+
+    /*
+     * Descriptor status input (from AXI CDMA core)
+     */
+    input  wire [M_TAG_WIDTH-1:0]          s_axis_desc_status_tag,
+    input  wire                            s_axis_desc_status_valid,
+
+    /*
+     * Descriptor input
+     */
+    input  wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_read_addr,
+    input  wire [PORTS*AXI_ADDR_WIDTH-1:0] s_axis_desc_write_addr,
+    input  wire [PORTS*LEN_WIDTH-1:0]      s_axis_desc_len,
+    input  wire [PORTS*S_TAG_WIDTH-1:0]    s_axis_desc_tag,
+    input  wire [PORTS-1:0]                s_axis_desc_valid,
+    output wire [PORTS-1:0]                s_axis_desc_ready,
+
+    /*
+     * Descriptor status output
+     */
+    output wire [PORTS*S_TAG_WIDTH-1:0]    m_axis_desc_status_tag,
+    output wire [PORTS-1:0]                m_axis_desc_status_valid
+);
+
+parameter CL_PORTS = $clog2(PORTS);
+
+// check configuration
+initial begin
+    if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
+        $error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH (instance %m)");
+        $finish;
+    end
+end
+
+// descriptor mux
+wire [PORTS-1:0] request;
+wire [PORTS-1:0] acknowledge;
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [CL_PORTS-1:0] grant_encoded;
+
+// internal datapath
+reg  [AXI_ADDR_WIDTH-1:0] m_axis_desc_read_addr_int;
+reg  [AXI_ADDR_WIDTH-1:0] m_axis_desc_write_addr_int;
+reg  [LEN_WIDTH-1:0]      m_axis_desc_len_int;
+reg  [M_TAG_WIDTH-1:0]    m_axis_desc_tag_int;
+reg                       m_axis_desc_valid_int;
+reg                       m_axis_desc_ready_int_reg = 1'b0;
+wire                      m_axis_desc_ready_int_early;
+
+assign s_axis_desc_ready = (m_axis_desc_ready_int_reg && grant_valid) << grant_encoded;
+
+// mux for incoming packet
+wire [AXI_ADDR_WIDTH-1:0] current_s_desc_read_addr   = s_axis_desc_read_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
+wire [AXI_ADDR_WIDTH-1:0] current_s_desc_write_addr  = s_axis_desc_write_addr[grant_encoded*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH];
+wire [LEN_WIDTH-1:0]      current_s_desc_len         = s_axis_desc_len[grant_encoded*LEN_WIDTH +: LEN_WIDTH];
+wire [S_TAG_WIDTH-1:0]    current_s_desc_tag         = s_axis_desc_tag[grant_encoded*S_TAG_WIDTH +: S_TAG_WIDTH];
+wire                      current_s_desc_valid       = s_axis_desc_valid[grant_encoded];
+wire                      current_s_desc_ready       = s_axis_desc_ready[grant_encoded];
+
+// arbiter instance
+arbiter #(
+    .PORTS(PORTS),
+    .TYPE(ARB_TYPE),
+    .BLOCK("ACKNOWLEDGE"),
+    .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+    .clk(clk),
+    .rst(rst),
+    .request(request),
+    .acknowledge(acknowledge),
+    .grant(grant),
+    .grant_valid(grant_valid),
+    .grant_encoded(grant_encoded)
+);
+
+assign request = s_axis_desc_valid & ~grant;
+assign acknowledge = grant & s_axis_desc_valid & s_axis_desc_ready;
+
+always @* begin
+    m_axis_desc_read_addr_int   = current_s_desc_read_addr;
+    m_axis_desc_write_addr_int  = current_s_desc_write_addr;
+    m_axis_desc_len_int         = current_s_desc_len;
+    m_axis_desc_tag_int         = {grant_encoded, current_s_desc_tag};
+    m_axis_desc_valid_int       = current_s_desc_valid && m_axis_desc_ready_int_reg && grant_valid;
+end
+
+// output datapath logic
+reg [AXI_ADDR_WIDTH-1:0]  m_axis_desc_read_addr_reg   = {AXI_ADDR_WIDTH{1'b0}};
+reg [AXI_ADDR_WIDTH-1:0]  m_axis_desc_write_addr_reg  = {AXI_ADDR_WIDTH{1'b0}};
+reg [LEN_WIDTH-1:0]       m_axis_desc_len_reg         = {LEN_WIDTH{1'b0}};
+reg [M_TAG_WIDTH-1:0]     m_axis_desc_tag_reg         = {M_TAG_WIDTH{1'b0}};
+reg                       m_axis_desc_valid_reg       = 1'b0, m_axis_desc_valid_next;
+
+reg [AXI_ADDR_WIDTH-1:0]  temp_m_axis_desc_read_addr_reg   = {AXI_ADDR_WIDTH{1'b0}};
+reg [AXI_ADDR_WIDTH-1:0]  temp_m_axis_desc_write_addr_reg  = {AXI_ADDR_WIDTH{1'b0}};
+reg [LEN_WIDTH-1:0]       temp_m_axis_desc_len_reg         = {LEN_WIDTH{1'b0}};
+reg [M_TAG_WIDTH-1:0]     temp_m_axis_desc_tag_reg         = {M_TAG_WIDTH{1'b0}};
+reg                       temp_m_axis_desc_valid_reg       = 1'b0, temp_m_axis_desc_valid_next;
+
+// datapath control
+reg store_axis_int_to_output;
+reg store_axis_int_to_temp;
+reg store_axis_temp_to_output;
+
+assign m_axis_desc_read_addr   = m_axis_desc_read_addr_reg;
+assign m_axis_desc_write_addr  = m_axis_desc_write_addr_reg;
+assign m_axis_desc_len         = m_axis_desc_len_reg;
+assign m_axis_desc_tag         = m_axis_desc_tag_reg;
+assign m_axis_desc_valid       = m_axis_desc_valid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axis_desc_ready_int_early = m_axis_desc_ready || (!temp_m_axis_desc_valid_reg && (!m_axis_desc_valid_reg || !m_axis_desc_valid_int));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axis_desc_valid_next = m_axis_desc_valid_reg;
+    temp_m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
+
+    store_axis_int_to_output = 1'b0;
+    store_axis_int_to_temp = 1'b0;
+    store_axis_temp_to_output = 1'b0;
+
+    if (m_axis_desc_ready_int_reg) begin
+        // input is ready
+        if (m_axis_desc_ready || !m_axis_desc_valid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axis_desc_valid_next = m_axis_desc_valid_int;
+            store_axis_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axis_desc_valid_next = m_axis_desc_valid_int;
+            store_axis_int_to_temp = 1'b1;
+        end
+    end else if (m_axis_desc_ready) begin
+        // input is not ready, but output is ready
+        m_axis_desc_valid_next = temp_m_axis_desc_valid_reg;
+        temp_m_axis_desc_valid_next = 1'b0;
+        store_axis_temp_to_output = 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axis_desc_valid_reg <= 1'b0;
+        m_axis_desc_ready_int_reg <= 1'b0;
+        temp_m_axis_desc_valid_reg <= 1'b0;
+    end else begin
+        m_axis_desc_valid_reg <= m_axis_desc_valid_next;
+        m_axis_desc_ready_int_reg <= m_axis_desc_ready_int_early;
+        temp_m_axis_desc_valid_reg <= temp_m_axis_desc_valid_next;
+    end
+
+    // datapath
+    if (store_axis_int_to_output) begin
+        m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
+        m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
+        m_axis_desc_len_reg <= m_axis_desc_len_int;
+        m_axis_desc_tag_reg <= m_axis_desc_tag_int;
+    end else if (store_axis_temp_to_output) begin
+        m_axis_desc_read_addr_reg <= temp_m_axis_desc_read_addr_reg;
+        m_axis_desc_write_addr_reg <= temp_m_axis_desc_write_addr_reg;
+        m_axis_desc_len_reg <= temp_m_axis_desc_len_reg;
+        m_axis_desc_tag_reg <= temp_m_axis_desc_tag_reg;
+    end
+
+    if (store_axis_int_to_temp) begin
+        temp_m_axis_desc_read_addr_reg <= m_axis_desc_read_addr_int;
+        temp_m_axis_desc_write_addr_reg <= m_axis_desc_write_addr_int;
+        temp_m_axis_desc_len_reg <= m_axis_desc_len_int;
+        temp_m_axis_desc_tag_reg <= m_axis_desc_tag_int;
+    end
+end
+
+// descriptor status demux
+reg [S_TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {S_TAG_WIDTH{1'b0}};
+reg [PORTS-1:0] m_axis_desc_status_valid_reg = {PORTS{1'b0}};
+
+assign m_axis_desc_status_tag = {PORTS{m_axis_desc_status_tag_reg}};
+assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axis_desc_status_valid_reg <= {PORTS{1'b0}};
+    end else begin
+        m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
+    end
+
+    m_axis_desc_status_tag_reg <= s_axis_desc_status_tag;
+end
+
+endmodule