Commit 68f7d33f authored by Hejing Li's avatar Hejing Li
Browse files

Merge branch 'master' into experiments

parents 7410c32e f5216010
...@@ -159,16 +159,16 @@ class SimpleComponent(Component): ...@@ -159,16 +159,16 @@ class SimpleComponent(Component):
async def process_out(self, lines, eof): async def process_out(self, lines, eof):
if self.verbose: if self.verbose:
for l in lines: for l in lines:
print(self.label, 'OUT:', lines) print(self.label, 'OUT:', lines, flush=True)
async def process_err(self, lines, eof): async def process_err(self, lines, eof):
if self.verbose: if self.verbose:
for l in lines: for l in lines:
print(self.label, 'ERR:', lines) print(self.label, 'ERR:', lines, flush=True)
async def terminated(self, rc): async def terminated(self, rc):
if self.verbose: if self.verbose:
print(self.label, 'TERMINATED:', rc) print(self.label, 'TERMINATED:', rc, flush=True)
if not self.canfail and rc != 0: if not self.canfail and rc != 0:
raise Exception('Command Failed: ' + str(self.cmd_parts)) raise Exception('Command Failed: ' + str(self.cmd_parts))
......
...@@ -200,7 +200,11 @@ class SlurmRuntime(Runtime): ...@@ -200,7 +200,11 @@ class SlurmRuntime(Runtime):
s = int(exp.timeout % 60) s = int(exp.timeout % 60)
f.write('#SBATCH --time=%02d:%02d:%02d\n' % (h, m, s)) f.write('#SBATCH --time=%02d:%02d:%02d\n' % (h, m, s))
f.write('python3 run.py --pickled %s\n' % (exp_path)) extra = ''
if self.verbose:
extra = '--verbose'
f.write('python3 run.py %s --pickled %s\n' % (extra, exp_path))
f.write('status=$?\n') f.write('status=$?\n')
if self.cleanup: if self.cleanup:
f.write('rm -rf %s\n' % (run.env.workdir)) f.write('rm -rf %s\n' % (run.env.workdir))
......
import math
class Simulator(object): class Simulator(object):
# number of cores required for this simulator # number of cores required for this simulator
def resreq_cores(self): def resreq_cores(self):
...@@ -103,7 +105,17 @@ class QemuHost(HostSim): ...@@ -103,7 +105,17 @@ class QemuHost(HostSim):
f'-m {self.node_config.memory} -smp {self.node_config.cores} ') f'-m {self.node_config.memory} -smp {self.node_config.cores} ')
if self.sync: if self.sync:
cmd += ' -cpu Skylake-Server -icount shift=0,sleep=off ' unit = self.cpu_freq[-3:]
if unit.lower() == 'ghz':
base = 0
elif unit.lower() == 'mhz':
base = 3
else:
raise Exception('cpu frequency specified in unsupported unit')
num = float(self.cpu_freq[:-3])
shift = base - int(math.ceil(math.log(num, 2)))
cmd += f' -cpu Skylake-Server -icount shift={shift},sleep=off '
else: else:
cmd += ' -cpu host -enable-kvm ' cmd += ' -cpu host -enable-kvm '
......
...@@ -10,7 +10,7 @@ import modes.nodeconfig as node ...@@ -10,7 +10,7 @@ import modes.nodeconfig as node
# net: switch/dumbbell/bridge # net: switch/dumbbell/bridge
# app: DCTCPm # app: DCTCPm
types_of_host = ['qemu', 'gt'] types_of_host = ['qemu', 'qt','gt']
types_of_nic = ['cv','cb','ib'] types_of_nic = ['cv','cb','ib']
types_of_net = ['dumbbell'] types_of_net = ['dumbbell']
types_of_app = ['DCTCPm'] types_of_app = ['DCTCPm']
...@@ -41,13 +41,19 @@ for h in types_of_host: ...@@ -41,13 +41,19 @@ for h in types_of_host:
e = exp.Experiment( h + '-' + c + '-' + 'dumbbell' + '-' + 'DCTCPm' + f'{k_val}' + f'-{mtu}') e = exp.Experiment( h + '-' + c + '-' + 'dumbbell' + '-' + 'DCTCPm' + f'{k_val}' + f'-{mtu}')
e.add_network(net) e.add_network(net)
e.checkpoint = True
# host # host
if h == 'qemu': if h == 'qemu':
host_class = sim.QemuHost host_class = sim.QemuHost
elif h == 'qt':
def qemu_timing():
h = sim.QemuHost()
h.sync = True
return h
host_class = qemu_timing
elif h == 'gt': elif h == 'gt':
host_class = sim.Gem5Host host_class = sim.Gem5Host
e.checkpoint = True
else: else:
raise NameError(h) raise NameError(h)
......
...@@ -34,22 +34,18 @@ static void sigusr1_handler(int dummy) ...@@ -34,22 +34,18 @@ static void sigusr1_handler(int dummy)
volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void) volatile union cosim_pcie_proto_d2h *Runner::d2h_alloc(void)
{ {
volatile union cosim_pcie_proto_d2h *msg = volatile union cosim_pcie_proto_d2h *msg;
nicsim_d2h_alloc(&nsparams, main_time); while ((msg = nicsim_d2h_alloc(&nsparams, main_time)) == NULL) {
if (msg == NULL) {
fprintf(stderr, "d2h_alloc: no entry available\n"); fprintf(stderr, "d2h_alloc: no entry available\n");
abort();
} }
return msg; return msg;
} }
volatile union cosim_eth_proto_d2n *Runner::d2n_alloc(void) volatile union cosim_eth_proto_d2n *Runner::d2n_alloc(void)
{ {
volatile union cosim_eth_proto_d2n *msg = volatile union cosim_eth_proto_d2n *msg;
nicsim_d2n_alloc(&nsparams, main_time); while ((msg = nicsim_d2n_alloc(&nsparams, main_time)) == NULL) {
if (msg == NULL) {
fprintf(stderr, "d2n_alloc: no entry available\n"); fprintf(stderr, "d2n_alloc: no entry available\n");
abort();
} }
return msg; return msg;
} }
......
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