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ycai
simbricks
Commits
5a3b22e0
Commit
5a3b22e0
authored
Dec 06, 2020
by
Hejing Li
Browse files
simple fix
parent
9638b07f
Changes
1
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1 changed file
with
12 additions
and
6 deletions
+12
-6
experiments/pyexps/dctcp.py
experiments/pyexps/dctcp.py
+12
-6
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experiments/pyexps/dctcp.py
View file @
5a3b22e0
...
@@ -25,7 +25,7 @@ link_latency_opt = '--LinkLatency=500ns '
...
@@ -25,7 +25,7 @@ link_latency_opt = '--LinkLatency=500ns '
cpu_freq
=
'5GHz'
cpu_freq
=
'5GHz'
cpu_freq_qemu
=
'2GHz'
cpu_freq_qemu
=
'2GHz'
#mtu = 4000
#mtu = 4000
sys_clock
=
'
2
GHz'
# if not set, default 1GHz
sys_clock
=
'
1
GHz'
# if not set, default 1GHz
ip_start
=
'192.168.64.1'
ip_start
=
'192.168.64.1'
...
@@ -57,13 +57,19 @@ for mtu in types_of_mtu:
...
@@ -57,13 +57,19 @@ for mtu in types_of_mtu:
return
h
return
h
host_class
=
qemu_timing
host_class
=
qemu_timing
elif
h
==
'gt'
:
elif
h
==
'gt'
:
host_class
=
sim
.
Gem5Host
def
gem5_timing
():
host_class
.
sys_clock
=
sys_clock
h
=
sim
.
Gem5Host
()
#h.sys_clock = sys_clock
return
h
host_class
=
gem5_timing
e
.
checkpoint
=
True
e
.
checkpoint
=
True
elif
h
==
'gO3'
:
elif
h
==
'gO3'
:
host_class
=
sim
.
Gem5Host
def
gem5_o3
():
host_class
.
cpu_type
=
'DerivO3CPU'
h
=
sim
.
Gem5Host
()
host_class
.
sys_clock
=
sys_clock
h
.
cpu_type
=
'DerivO3CPU'
h
.
sys_clock
=
sys_clock
return
h
host_class
=
gem5_o3
e
.
checkpoint
=
True
e
.
checkpoint
=
True
else
:
else
:
raise
NameError
(
h
)
raise
NameError
(
h
)
...
...
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