corundum: checkpoint

corundum/corundum_verilator.cpp

@@ -630,10 +630,10 @@ int main(int argc, char *argv[])
             top->ctrl_dma_ram_rd_cmd_sel,
             top->ctrl_dma_ram_rd_cmd_addr,
             top->ctrl_dma_ram_rd_cmd_valid,
-            top->ctrl_dma_ram_rd_cmd_ready,
+            top->ctrl_dma_ram_rd_resp_ready,
             top->ctrl_dma_ram_rd_resp_data,
-            top->ctrl_dma_ram_rd_resp_valid,
-            top->ctrl_dma_ram_rd_resp_ready);
+            top->ctrl_dma_ram_rd_cmd_ready,
+            top->ctrl_dma_ram_rd_resp_valid);
     MemWritePort p_mem_write_data_dma(
             top->data_dma_ram_wr_cmd_sel,
             top->data_dma_ram_wr_cmd_be,
@@ -645,10 +645,10 @@ int main(int argc, char *argv[])
             top->data_dma_ram_rd_cmd_sel,
             top->data_dma_ram_rd_cmd_addr,
             top->data_dma_ram_rd_cmd_valid,
-            top->data_dma_ram_rd_cmd_ready,
+            top->data_dma_ram_rd_resp_ready,
             top->data_dma_ram_rd_resp_data,
-            top->data_dma_ram_rd_resp_valid,
-            top->data_dma_ram_rd_resp_ready);
+            top->data_dma_ram_rd_cmd_ready,
+            top->data_dma_ram_rd_resp_valid);
 
     DMAPorts p_dma_read_ctrl(
             top->m_axis_ctrl_dma_read_desc_dma_addr,
@@ -693,12 +693,16 @@ int main(int argc, char *argv[])
 
 
     MMIOInterface mmio(*top);
-    MemReader mem_control_reader(p_mem_read_ctrl_dma);
+
     MemWriter mem_control_writer(p_mem_write_ctrl_dma);
+    MemReader mem_control_reader(p_mem_read_ctrl_dma);
     MemWriter mem_data_writer(p_mem_write_data_dma);
+    MemReader mem_data_reader(p_mem_read_data_dma);
+
     DMAReader dma_read_ctrl("read ctrl", p_dma_read_ctrl, mem_control_writer);
+    DMAWriter dma_write_ctrl("write ctrl", p_dma_write_ctrl, mem_control_reader);
     DMAReader dma_read_data("read data", p_dma_read_data, mem_data_writer);
-    //DMAEngine dma_write_ctrl(*top, "write ctrl", false, mem_writer/*should be reader*/,
+    DMAWriter dma_write_data("write data", p_dma_write_data, mem_data_reader);
 
     EthernetTx tx(*top);
 
@@ -721,17 +725,25 @@ int main(int argc, char *argv[])
         top->eval();
 
         mmio.step();
+
         dma_read_ctrl.step();
+        dma_write_ctrl.step();
         dma_read_data.step();
+        dma_write_data.step();
+
         mem_control_writer.step();
+        mem_control_reader.step();
         mem_data_writer.step();
-        //dma_write_ctrl.step();
+        mem_data_reader.step();
         tx.step();
 
         /* raising edge */
         top->clk = !top->clk;
         main_time++;
 
+        //top->s_axis_tx_ptp_ts_96 = main_time;
+        top->s_axis_tx_ptp_ts_valid = 1;
+
         top->eval();
     }
     report_outputs(top);

corundum/dma.cpp

@@ -48,3 +48,51 @@ void DMAReader::mem_op_complete(DMAOp *op)
     completed.push_back(op);
     //std::cout << "dma[" << label << "] mem complete " << op->dma_addr << std::endl;
 }
+
+
+
+void DMAWriter::step()
+{
+    p.dma_ready = 1;
+    if (p.dma_valid) {
+        DMAOp *op = new DMAOp;
+        op->engine = this;
+        op->dma_addr = p.dma_addr;
+        op->ram_sel = p.dma_ram_sel;
+        op->ram_addr = p.dma_ram_addr;
+        op->len = p.dma_len;
+        op->tag = p.dma_tag;
+        op->write = true;
+        pending.insert(op);
+        std::cout << "dma write [" << label << "] op " << op->dma_addr << " -> " <<
+            op->ram_sel << ":" << op->ram_addr <<
+            "   len=" << op->len << "   tag=" << (int) op->tag << std::endl;
+
+        mr.op_issue(op);
+    }
+
+    p.dma_status_valid = 0;
+    if (!completed.empty()) {
+        DMAOp *op = completed.front();
+        completed.pop_front();
+
+        std::cout << "dma write [" << label << "] status complete " << op->dma_addr << std::endl;
+
+        p.dma_status_valid = 1;
+        p.dma_status_tag = op->tag;
+        pending.erase(op);
+        delete op;
+    }
+}
+
+void DMAWriter::pci_op_complete(DMAOp *op)
+{
+    std::cout << "dma write [" << label << "] pci complete " << op->dma_addr << std::endl;
+    completed.push_back(op);
+}
+
+void DMAWriter::mem_op_complete(DMAOp *op)
+{
+    std::cout << "dma write [" << label << "] mem complete " << op->dma_addr << std::endl;
+    pci_dma_issue(op);
+}

corundum/dma.h

@@ -11,6 +11,7 @@
 
 class DMAEngine;
 class MemWriter;
+class MemReader;
 
 struct DMAPorts {
     /* inputs to DMA engine */
@@ -82,4 +83,23 @@ class DMAReader : public DMAEngine {
         void step();
 };
 
+class DMAWriter : public DMAEngine {
+    protected:
+        std::set<DMAOp *> pending;
+        std::deque<DMAOp *> completed;
+        const char *label;
+        MemReader &mr;
+
+    public:
+        DMAWriter(const char *label_, DMAPorts &p_, MemReader &mr_)
+            : DMAEngine(p_), label(label_), mr(mr_)
+        {
+        }
+
+        virtual void pci_op_complete(DMAOp *op);
+        virtual void mem_op_complete(DMAOp *op);
+        void step();
+};
+
+
 #endif /* ndef DMA_H_ */

corundum/mem.cpp

@@ -79,3 +79,74 @@ void MemWriter::op_issue(DMAOp *op)
     //std::cerr << "enqueued write to " << op->ram_addr << std::endl;
     pending.push_back(op);
 }
+
+
+
+
+void MemReader::step()
+{
+    size_t data_byte_width = DATA_WIDTH / 8;
+
+    if (cur && p.mem_resvalid) {
+        std::cerr << "completed read from: " << cur->ram_addr << std::endl;
+        p.mem_valid = 0;
+        p.mem_resready = 0;
+
+        size_t off = cur->ram_addr % data_byte_width;
+        for (size_t i = 0; i < cur->len; i++, off++) {
+            size_t byte_off = off % 4;
+            cur->data[i] = (p.mem_data[off / 4] >> (byte_off * 8)) & 0xff;
+        }
+
+        cur->engine->mem_op_complete(cur);
+        cur = 0;
+    }
+
+    if (!cur && !pending.empty()) {
+        cur = pending.front();
+        pending.pop_front();
+
+        std::cerr << "issuing read from " << cur->ram_addr << std::endl;
+
+        size_t data_offset = cur->ram_addr % data_byte_width;
+
+        if (cur->len > data_byte_width - data_offset) {
+            std::cerr << "MemReader::step: cannot be written in one cycle TODO" << std::endl;
+            throw "unsupported";
+        }
+
+        /* first reset everything */
+        p.mem_sel = 0;
+        p.mem_addr[0] = p.mem_addr[1] = p.mem_addr[2] = 0;
+        p.mem_valid = 0x0;
+
+
+        /* put data bytes in the right places */
+        size_t off = data_offset;
+        for (size_t i = 0; i < cur->len; i++, off++) {
+            size_t byte_off = off % 4;
+            p.mem_valid |= (1 << (off / (SEG_WIDTH / 8)));
+        }
+
+        uint64_t seg_addr = cur->ram_addr / data_byte_width;
+        size_t seg_addr_bits = 12;
+
+        // iterate over the address bit by bit
+        for (size_t i = 0; i < seg_addr_bits; i++) {
+            uint32_t bit = ((seg_addr >> i) & 0x1);
+            // iterate over the segments
+            for (size_t j = 0; j < SEG_COUNT; j++) {
+                size_t dst_bit = j * seg_addr_bits + i;
+                p.mem_addr[dst_bit / 32] |= (bit << (dst_bit % 32));
+            }
+        }
+
+        p.mem_resready = 1;
+    }
+}
+
+void MemReader::op_issue(DMAOp *op)
+{
+    std::cerr << "enqueued read from " << op->ram_addr << std::endl;
+    pending.push_back(op);
+}

corundum/mem.h

@@ -55,11 +55,18 @@ class MemReader {
     protected:
         MemReadPort &p;
 
+        std::deque<DMAOp *> pending;
+        DMAOp *cur;
+        size_t cur_off;
+
     public:
         MemReader(MemReadPort &p_)
-            : p(p_)
+            : p(p_), cur(0), cur_off(0)
         {
         }
+
+        void step();
+        void op_issue(DMAOp *op);
 };
 
 class MemWriter {