add simulator list to simulation class. add simulator to this list at...

add simulator list to simulation class. add simulator to this list at initialization. & fix some syntex errors

experiments/simbricks/orchestration/simulation/base.py

@@ -57,6 +57,7 @@ class Simulator(utils_base.IdObj):
         self.extra_deps: list[Simulator] = []
         self._simulation: sim_base.Simulation = simulation
         self._components: set[sys_conf.Component] = set()
+        simulation.add_sim(self)
 
     @staticmethod
     def filter_sockets(
@@ -121,7 +122,7 @@ class Simulator(utils_base.IdObj):
         """Commands to prepare execution of this simulator."""
         return []
 
-    def add(self, comp: sys_base.Component) -> None:
+    def add(self, comp: sys_conf.Component) -> None:
         if comp in self._components:
             raise Exception("cannot add the same specification twice to a simulator")
         self._components.add(comp)
@@ -273,6 +274,14 @@ class Simulation(utils_base.IdObj):
         self._chan_map: dict[sys_conf.Channel, sim_chan.Channel] = {}
         """Channel spec and its instanciation"""
 
+        self._sim_list: list[Simulator] = []
+        """Channel spec and its instanciation"""
+
+    def add_sim (self, sim: Simulator):
+        if sim in self._sim_list:
+            raise Exception("Simulaotr is already added")
+        self._sim_list.append(sim)
+
     def add_spec_sim_map(self, sys: sys_conf.Component, sim: Simulator):
         """Add a mapping from specification to simulation instance"""
         if sys in self._sys_sim_map:
@@ -290,10 +299,8 @@ class Simulation(utils_base.IdObj):
         self._chan_map[chan] = channel
         return channel
 
-    def all_simulators(self) -> set[Simulator]:
-        """Returns all simulators defined to run in this experiment."""
-        simulators = set(map(lambda kv: kv[1], self._sys_sim_map.items()))
-        return simulators
+    def all_simulators(self) -> list[Simulator]:
+        return self._sim_list
 
     def resreq_mem(self) -> int:
         """Memory required to run all simulators in this experiment."""

experiments/simbricks/orchestration/simulation/host.py

@@ -56,9 +56,7 @@ class HostSim(sim_base.Simulator):
     def add(self, host: 'Host'):
         self.hosts.append(host)
         self.name = f'{self._id}'
-        # TODO: FIXME, call super method...
-        # self.experiment.add_host(self)
-        # self.experiment.sys_sim_map[host] = self
+        self._simulation.add_spec_sim_map(host, self)
 
     def config_str(self) -> str:
         return []

experiments/simbricks/orchestration/simulation/net/base.py

@@ -63,7 +63,7 @@ class WireNet(NetSim):
         self._relative_pcap_file_path: str | None = "relative_pcap_file_path"
 
     def add(self, wire: eth.EthWire):
-        base_utils.has_expected_type(wire, eth.EthWire())
+        base_utils.has_expected_type(wire, eth.EthWire)
         if len(self._components) > 1:
             raise Exception(
                 "can only add a single wire component to the WireNet simulator"
@@ -104,7 +104,7 @@ class SwitchNet(NetSim):
         self._relative_pcap_file_path: str | None = relative_pcap_file_path
 
     def add(self, switch_spec: eth.EthSwitch):
-        base_utils.has_expected_type(wire, eth.EthSwitch())
+        base_utils.has_expected_type(switch_spec, eth.EthSwitch)
         if len(self._components) > 1:
             raise Exception("can only add a single switch component to the SwitchNet")
         super().add(switch_spec)

experiments/simbricks/orchestration/simulation/pcidev.py

@@ -64,10 +64,7 @@ class NICSim(PCIDevSim):
 
     def add(self, nic: sys_conf.SimplePCIeNIC):
         self.nics.append(nic)
-        # nic.sim = self
-        # TODO: FIXME, call super method...
-        #self.experiment.add_nic(self)
-        #self.experiment.sys_sim_map[nic] = self
+        self.experiment.add_spec_sim_map(nic, self)
         self.name = f'{nic._id}'
 
     def basic_args(self, env: ExpEnv, extra: tp.Optional[str] = None) -> str: