i40e: plumbing for lan queue manager module

i40e_bm/Makefile

@@ -3,7 +3,7 @@ CPPFLAGS += -I../libnicbm/include/
 CFLAGS += -Wall -Wextra -Wno-unused-parameter -O3 -g
 LDFLGAS = -g
 
-OBJS := i40e_bm.o i40e_queues.o i40e_adminq.o i40e_hmc.o
+OBJS := i40e_bm.o i40e_queues.o i40e_adminq.o i40e_hmc.o i40e_lan.o
 
 all: i40e_bm
 

i40e_bm/i40e_bm.cc

@@ -13,7 +13,7 @@ namespace i40e {
 
 i40e_bm::i40e_bm()
     : pf_atq(*this, regs.pf_atqba, regs.pf_atqlen, regs.pf_atqh, regs.pf_atqt),
-    hmc(*this), shram(*this)
+    hmc(*this), shram(*this), lanmgr(*this, NUM_QUEUES)
 {
     memset(&regs, 0, sizeof(regs));
 }
@@ -342,11 +342,15 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
     } else if (addr >= I40E_QTX_ENA(0) &&
             addr <= I40E_QTX_ENA(NUM_QUEUES - 1))
     {
-        regs.qtx_ena[(addr - I40E_QTX_ENA(0)) / 4] = val;
+        size_t idx = (addr - I40E_QTX_ENA(0)) / 4;
+        regs.qtx_ena[idx] = val;
+        lanmgr.qena_updated(idx, false);
     } else if (addr >= I40E_QTX_TAIL(0) &&
             addr <= I40E_QTX_TAIL(NUM_QUEUES - 1))
     {
-        regs.qtx_tail[(addr - I40E_QTX_TAIL(0)) / 4] = val;
+        size_t idx = (addr - I40E_QTX_TAIL(0)) / 4;
+        regs.qtx_tail[idx] = val;
+        lanmgr.tail_updated(idx, false);
     } else if (addr >= I40E_QINT_RQCTL(0) &&
             addr <= I40E_QINT_RQCTL(NUM_QUEUES - 1))
     {
@@ -354,11 +358,15 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
     } else if (addr >= I40E_QRX_ENA(0) &&
             addr <= I40E_QRX_ENA(NUM_QUEUES - 1))
     {
-        regs.qrx_ena[(addr - I40E_QRX_ENA(0)) / 4] = val;
+        size_t idx = (addr - I40E_QRX_ENA(0)) / 4;
+        regs.qrx_ena[idx] = val;
+        lanmgr.qena_updated(idx, true);
     } else if (addr >= I40E_QRX_TAIL(0) &&
             addr <= I40E_QRX_TAIL(NUM_QUEUES - 1))
     {
-        regs.qrx_tail[(addr - I40E_QRX_TAIL(0)) / 4] = val;
+        size_t idx = (addr - I40E_QRX_TAIL(0)) / 4;
+        regs.qrx_tail[idx] = val;
+        lanmgr.tail_updated(idx, true);
     } else if (addr >= I40E_GLQF_HKEY(0) &&
             addr <= I40E_GLQF_HKEY(I40E_GLQF_HKEY_MAX_INDEX))
     {

i40e_bm/i40e_bm.h

@@ -152,6 +152,16 @@ class host_mem_cache {
         void issue_mem_op(mem_op &op);
 };
 
+// rx tx management
+class lan {
+    protected:
+        i40e_bm &dev;
+        const size_t num_qs;
+    public:
+        lan(i40e_bm &dev, size_t num_qs);
+        void qena_updated(uint16_t idx, bool rx);
+        void tail_updated(uint16_t idx, bool rx);
+};
 
 class shadow_ram {
     protected:
@@ -166,8 +176,9 @@ class shadow_ram {
 
 class i40e_bm : public nicbm::Runner::Device {
 protected:
-    friend class shadow_ram;
     friend class queue_admin_tx;
+    friend class host_mem_cache;
+    friend class shadow_ram;
 
     static const unsigned BAR_REGS = 0;
     static const unsigned BAR_IO = 2;
@@ -235,6 +246,7 @@ protected:
     queue_admin_tx pf_atq;
     host_mem_cache hmc;
     shadow_ram shram;
+    lan lanmgr;
 
     /** Read from the I/O bar */
     virtual uint32_t reg_io_read(uint64_t addr);

i40e_bm/i40e_lan.cc

+#include <stdlib.h>
+#include <string.h>
+#include <cassert>
+#include <iostream>
+
+#include "i40e_bm.h"
+
+#include "i40e_base_wrapper.h"
+
+using namespace i40e;
+
+extern nicbm::Runner *runner;
+
+lan::lan(i40e_bm &dev_, size_t num_qs_)
+    : dev(dev_), num_qs(num_qs_)
+{
+}
+
+void lan::qena_updated(uint16_t idx, bool rx)
+{
+}
+
+void lan::tail_updated(uint16_t idx, bool rx)
+{
+}