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Commit 2d93957b authored by Antoine Kaufmann's avatar Antoine Kaufmann
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i40e: disable debug messages by default

parent 7e4f44db
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Inline Side-by-side
Showing with 261 additions and 79 deletions
i40e_bm/i40e_adminq.cc
View file @ 2d93957b
......@@ -13,7 +13,7 @@ extern nicbm::Runner *runner;
queue_admin_tx::queue_admin_tx(i40e_bm &dev_, uint64_t &reg_base_,
uint32_t &reg_len_, uint32_t &reg_head_, uint32_t &reg_tail_)
: queue_base(reg_head_, reg_tail_), dev(dev_), reg_base(reg_base_),
: queue_base("atx", reg_head_, reg_tail_), dev(dev_), reg_base(reg_base_),
reg_len(reg_len_)
{
desc_len = 32;
......@@ -31,10 +31,15 @@ void queue_admin_tx::reg_updated()
len = (reg_len & I40E_GL_ATQLEN_ATQLEN_MASK) >> I40E_GL_ATQLEN_ATQLEN_SHIFT;
if (!enabled && (reg_len & I40E_GL_ATQLEN_ATQENABLE_MASK)) {
std::cerr << "enable atq base=" << base << " len=" << len << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: enable base=" << base << " len=" << len <<
std::endl;
#endif
enabled = true;
} else if (enabled && !(reg_len & I40E_GL_ATQLEN_ATQENABLE_MASK)) {
std::cerr << "disable atq" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: disable" << std::endl;
#endif
enabled = false;
}
......@@ -92,8 +97,10 @@ void queue_admin_tx::admin_desc_ctx::prepare()
if ((d->flags & I40E_AQ_FLAG_RD)) {
uint64_t addr = d->params.external.addr_low |
(((uint64_t) d->params.external.addr_high) << 32);
std::cerr << " desc with buffer opc=" << d->opcode << " addr=" << addr
<< std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: desc with buffer opc=" << d->opcode << " addr=" <<
addr << std::endl;
#endif
data_fetch(addr, d->datalen);
} else {
prepared();
......@@ -102,10 +109,14 @@ void queue_admin_tx::admin_desc_ctx::prepare()
void queue_admin_tx::admin_desc_ctx::process()
{
std::cerr << "descriptor " << index << " fetched" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: descriptor " << index << " fetched" << std::endl;
#endif
if (d->opcode == i40e_aqc_opc_get_version) {
std::cerr << " get version" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: get version" << std::endl;
#endif
struct i40e_aqc_get_version *gv =
reinterpret_cast<struct i40e_aqc_get_version *>(d->params.raw);
gv->rom_ver = 0;
......@@ -117,30 +128,42 @@ void queue_admin_tx::admin_desc_ctx::process()
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_request_resource) {
std::cerr << " request resource" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: request resource" << std::endl;
#endif
struct i40e_aqc_request_resource *rr =
reinterpret_cast<struct i40e_aqc_request_resource *>(
d->params.raw);
rr->timeout = 180000;
std::cerr << " res_id=" << rr->resource_id << std::endl;
std::cerr << " res_nu=" << rr->resource_number << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: res_id=" << rr->resource_id << std::endl;
std::cerr << "atq: res_nu=" << rr->resource_number << std::endl;
#endif
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_release_resource) {
std::cerr << " release resource" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: release resource" << std::endl;
#endif
#ifdef DEBUG_ADMINQ
struct i40e_aqc_request_resource *rr =
reinterpret_cast<struct i40e_aqc_request_resource *>(
d->params.raw);
std::cerr << " res_id=" << rr->resource_id << std::endl;
std::cerr << " res_nu=" << rr->resource_number << std::endl;
std::cerr << "atq: res_id=" << rr->resource_id << std::endl;
std::cerr << "atq: res_nu=" << rr->resource_number << std::endl;
#endif
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_clear_pxe_mode) {
std::cerr << " clear PXE mode" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: clear PXE mode" << std::endl;
#endif
dev.regs.gllan_rctl_0 &= ~I40E_GLLAN_RCTL_0_PXE_MODE_MASK;
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_list_func_capabilities ||
d->opcode == i40e_aqc_opc_list_dev_capabilities)
{
std::cerr << " get dev/fun caps" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: get dev/fun caps" << std::endl;
#endif
struct i40e_aqc_list_capabilites *lc =
reinterpret_cast<struct i40e_aqc_list_capabilites *>(
d->params.raw);
......@@ -156,35 +179,47 @@ void queue_admin_tx::admin_desc_ctx::process()
size_t num_caps = sizeof(caps) / sizeof(caps[0]);
if (sizeof(caps) <= d->datalen) {
std::cerr << " data fits" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: data fits" << std::endl;
#endif
// data fits within the buffer
lc->count = num_caps;
desc_complete_indir(0, caps, sizeof(caps));
} else {
std::cerr << " data doesn't fit" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: data doesn't fit" << std::endl;
#endif
// data does not fit
d->datalen = sizeof(caps);
desc_complete(I40E_AQ_RC_ENOMEM);
}
} else if (d->opcode == i40e_aqc_opc_lldp_stop) {
std::cerr << " lldp stop" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: lldp stop" << std::endl;
#endif
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_mac_address_read) {
std::cerr << " read mac" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: read mac" << std::endl;
#endif
struct i40e_aqc_mac_address_read *ar =
reinterpret_cast<struct i40e_aqc_mac_address_read *>(
d->params.raw);
struct i40e_aqc_mac_address_read_data ard;
uint64_t mac = runner->get_mac_addr();
std::cerr << " mac = " << mac << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: mac = " << mac << std::endl;
#endif
memcpy(ard.pf_lan_mac, &mac, 6);
memcpy(ard.port_mac, &mac, 6);
ar->command_flags = I40E_AQC_LAN_ADDR_VALID | I40E_AQC_PORT_ADDR_VALID;
desc_complete_indir(0, &ard, sizeof(ard));
} else if (d->opcode == i40e_aqc_opc_get_phy_abilities) {
std::cerr << " get phy abilities" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: get phy abilities" << std::endl;
#endif
struct i40e_aq_get_phy_abilities_resp par;
memset(&par, 0, sizeof(par));
......@@ -199,7 +234,9 @@ void queue_admin_tx::admin_desc_ctx::process()
desc_complete_indir(0, &par, sizeof(par), 0, true);
} else if (d->opcode == i40e_aqc_opc_get_link_status) {
std::cerr << " link status" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: link status" << std::endl;
#endif
struct i40e_aqc_get_link_status *gls =
reinterpret_cast<struct i40e_aqc_get_link_status *>(
d->params.raw);
......@@ -219,7 +256,9 @@ void queue_admin_tx::admin_desc_ctx::process()
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_get_switch_config) {
std::cerr << " get switch config" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: get switch config" << std::endl;
#endif
struct i40e_aqc_switch_seid *sw = reinterpret_cast<
struct i40e_aqc_switch_seid *>(d->params.raw);
struct i40e_aqc_get_switch_config_header_resp hr;
......@@ -267,7 +306,10 @@ void queue_admin_tx::admin_desc_ctx::process()
memset(&hr, 0, sizeof(hr));
hr.num_reported = report;
hr.num_total = cnt;
std::cerr << " report=" << report << " cnt=" << cnt << " seid=" << sw->seid << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: report=" << report << " cnt=" << cnt <<
" seid=" << sw->seid << std::endl;
#endif
// create temporary contiguous buffer
size_t buflen = sizeof(hr) + sizeof(els[0]) * report;
......@@ -277,7 +319,9 @@ void queue_admin_tx::admin_desc_ctx::process()
desc_complete_indir(0, buf, buflen);
} else if (d->opcode == i40e_aqc_opc_set_switch_config) {
std::cerr << " set switch config" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: set switch config" << std::endl;
#endif
/* TODO: lots of interesting things here like l2 filtering etc. that are
* relevant.
struct i40e_aqc_set_switch_config *sc =
......@@ -286,7 +330,9 @@ void queue_admin_tx::admin_desc_ctx::process()
*/
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_get_vsi_parameters) {
std::cerr << " get vsi parameters" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: get vsi parameters" << std::endl;
#endif
/*struct i40e_aqc_add_get_update_vsi *v =
reinterpret_cast<struct i40e_aqc_add_get_update_vsi *>(
d->params.raw);*/
......@@ -299,32 +345,44 @@ void queue_admin_tx::admin_desc_ctx::process()
I40E_AQ_VSI_PROP_SCHED_VALID;
desc_complete_indir(0, &pd, sizeof(pd));
} else if (d->opcode == i40e_aqc_opc_update_vsi_parameters) {
std::cerr << " update vsi parameters" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: update vsi parameters" << std::endl;
#endif
/* TODO */
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_set_dcb_parameters) {
std::cerr << " set dcb parameters" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: set dcb parameters" << std::endl;
#endif
/* TODO */
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_configure_vsi_bw_limit) {
std::cerr << " configure vsi bw limit" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: configure vsi bw limit" << std::endl;
#endif
desc_complete(0);
} else if (d->opcode == i40e_aqc_opc_query_vsi_bw_config) {
std::cerr << " query vsi bw config" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: query vsi bw config" << std::endl;
#endif
struct i40e_aqc_query_vsi_bw_config_resp bwc;
memset(&bwc, 0, sizeof(bwc));
for (size_t i = 0; i < 8; i++)
bwc.qs_handles[i] = 0xffff;
desc_complete_indir(0, &bwc, sizeof(bwc));
} else if (d->opcode == i40e_aqc_opc_query_vsi_ets_sla_config) {
std::cerr << " query vsi ets sla config" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: query vsi ets sla config" << std::endl;
#endif
struct i40e_aqc_query_vsi_ets_sla_config_resp sla;
memset(&sla, 0, sizeof(sla));
for (size_t i = 0; i < 8; i++)
sla.share_credits[i] = 127;
desc_complete_indir(0, &sla, sizeof(sla));
} else if (d->opcode == i40e_aqc_opc_remove_macvlan) {
std::cerr << " remove macvlan" << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: remove macvlan" << std::endl;
#endif
struct i40e_aqc_macvlan *m = reinterpret_cast<
struct i40e_aqc_macvlan *>(d->params.raw);
struct i40e_aqc_remove_macvlan_element_data *rve =
......@@ -335,7 +393,9 @@ void queue_admin_tx::admin_desc_ctx::process()
desc_complete_indir(0, data, d->datalen);
} else {
std::cerr << " uknown opcode=" << d->opcode << std::endl;
#ifdef DEBUG_ADMINQ
std::cerr << "atq: uknown opcode=" << d->opcode << std::endl;
#endif
//desc_complete(I40E_AQ_RC_ESRCH);
desc_complete(0);
}
......
i40e_bm/i40e_bm.cc
View file @ 2d93957b
......@@ -39,13 +39,17 @@ void i40e_bm::setup_intro(struct cosim_pcie_proto_dev_intro &di)
void i40e_bm::dma_complete(nicbm::DMAOp &op)
{
dma_base &dma = dynamic_cast<dma_base &>(op);
#ifdef DEBUG_DEV
std::cerr << "dma_complete(" << &op << ")" << std::endl;
#endif
dma.done();
}
void i40e_bm::eth_rx(uint8_t port, const void *data, size_t len)
{
#ifdef DEBUG_DEV
std::cerr << "i40e: received packet len=" << len << std::endl;
#endif
lanmgr.packet_received(data, len);
}
......@@ -353,8 +357,10 @@ uint32_t i40e_bm::reg_mem_read32(uint64_t addr)
break;
default:
#ifdef DEBUG_DEV
std::cerr << "unhandled mem read addr=" << std::hex << addr
<< std::endl;
#endif
break;
}
}
......@@ -529,8 +535,10 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
break;
default:
#ifdef DEBUG_DEV
std::cerr << "unhandled mem write addr=" << std::hex << addr
<< " val=" << val << std::endl;
#endif
break;
}
}
......@@ -538,7 +546,9 @@ void i40e_bm::reg_mem_write32(uint64_t addr, uint32_t val)
void i40e_bm::reset(bool indicate_done)
{
#ifdef DEBUG_DEV
std::cout << "reset triggered" << std::endl;
#endif
pf_atq.reset();
hmc.reset();
......@@ -567,8 +577,10 @@ void shadow_ram::reg_updated()
>> I40E_GLNVM_SRCTL_ADDR_SHIFT;
is_write = (val & I40E_GLNVM_SRCTL_WRITE_MASK);
#ifdef DEBUG_DEV
std::cerr << "shadow ram op addr=" << std::hex << addr << " w=" << is_write
<< std::endl;
#endif
if (is_write) {
write(addr,
......@@ -602,8 +614,10 @@ uint16_t shadow_ram::read(uint16_t addr)
return 0xbaba;
default:
#ifdef DEBUG_DEV
std::cerr << "TODO shadow memory read addr=" << std::hex << addr
<< std::endl;
#endif
break;
}
......@@ -612,8 +626,10 @@ uint16_t shadow_ram::read(uint16_t addr)
void shadow_ram::write(uint16_t addr, uint16_t val)
{
#ifdef DEBUG_DEV
std::cerr << "TODO shadow memory write addr=" << std::hex << addr <<
" val=" << val << std::endl;
#endif
}
} //namespace i40e
......
i40e_bm/i40e_bm.h
View file @ 2d93957b
......@@ -7,6 +7,12 @@ extern "C" {
}
#include <nicbm.h>
//#define DEBUG_DEV
//#define DEBUG_ADMINQ
//#define DEBUG_LAN
//#define DEBUG_HMC
//#define DEBUG_QUEUES
struct i40e_aq_desc;
struct i40e_tx_desc;
......@@ -127,6 +133,7 @@ class queue_base {
virtual void done();
};
std::string qname;
desc_ctx *desc_ctxs[MAX_ACTIVE_DESCS];
uint32_t active_first_pos;
uint32_t active_first_idx;
......@@ -164,7 +171,8 @@ class queue_base {
// called by dma op when writeback has completed
void writeback_done(uint32_t first_pos, uint32_t cnt);
public:
queue_base(uint32_t &reg_head_, uint32_t &reg_tail_);
queue_base(const std::string &qname_, uint32_t &reg_head_,
uint32_t &reg_tail_);
virtual void reset();
void reg_updated();
bool is_enabled();
......@@ -266,7 +274,8 @@ class lan_queue_base : public queue_base {
uint32_t reg_dummy_head;
lan_queue_base(lan &lanmgr_, uint32_t &reg_tail, size_t idx_,
lan_queue_base(lan &lanmgr_, const std::string &qtype, uint32_t &reg_tail,
size_t idx_,
uint32_t &reg_ena_, uint32_t &fpm_basereg, uint32_t &reg_intqctl,
uint16_t ctx_size);
virtual void reset();
......
i40e_bm/i40e_hmc.cc
View file @ 2d93957b
......@@ -39,7 +39,9 @@ void host_mem_cache::reg_updated(uint64_t addr)
uint32_t hi = dev.regs.pfhmc_sddatahigh;
if ((cmd & I40E_PFHMC_SDCMD_PMSDWR_MASK)) {
// write
#ifdef DEBUG_HMC
std::cerr << "hmc: writing descriptor " << idx << std::endl;
#endif
segs[idx].addr = ((lo & I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK) >>
I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) << 12;
......@@ -49,12 +51,16 @@ void host_mem_cache::reg_updated(uint64_t addr)
segs[idx].valid = !!(lo & I40E_PFHMC_SDDATALOW_PMSDVALID_MASK);
segs[idx].direct = !!(lo & I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK);
#ifdef DEBUG_HMC
std::cerr << " addr=" << segs[idx].addr << " pgcount=" <<
segs[idx].pgcount << " valid=" << segs[idx].valid <<
" direct=" << segs[idx].direct << std::endl;
#endif
} else {
// read
#ifdef DEBUG_HMC
std::cerr << "hmc: reading descriptor " << idx << std::endl;
#endif
dev.regs.pfhmc_sddatalow = ((segs[idx].addr >> 12) <<
I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) &
......@@ -108,7 +114,9 @@ void host_mem_cache::issue_mem_op(mem_op &op)
op.failed = false;
op.dma_addr = seg->addr + dir_off;
#ifdef DEBUG_HMC
std::cerr << "hmc issue_mem_op: hmc_addr=" << addr << " dma_addr=" <<
op.dma_addr << " len=" << op.len << std::endl;
#endif
runner->issue_dma(op);
}
i40e_bm/i40e_lan.cc
View file @ 2d93957b
......@@ -37,7 +37,9 @@ void lan::reset()
void lan::qena_updated(uint16_t idx, bool rx)
{
#ifdef DEBUG_LAN
std::cerr << "lan: qena updated idx=" << idx << " rx=" << rx << std::endl;
#endif
uint32_t &reg = (rx ? dev.regs.qrx_ena[idx] : dev.regs.qtx_ena[idx]);
lan_queue_base &q = (rx ? static_cast<lan_queue_base &>(*rxqs[idx]) :
static_cast<lan_queue_base &>(*txqs[idx]));
......@@ -51,7 +53,9 @@ void lan::qena_updated(uint16_t idx, bool rx)
void lan::tail_updated(uint16_t idx, bool rx)
{
#ifdef DEBUG_LAN
std::cerr << "lan: tail updated idx=" << idx << " rx=" << rx << std::endl;
#endif
lan_queue_base &q = (rx ? static_cast<lan_queue_base &>(*rxqs[idx]) :
static_cast<lan_queue_base &>(*txqs[idx]));
......@@ -62,16 +66,20 @@ void lan::tail_updated(uint16_t idx, bool rx)
void lan::packet_received(const void *data, size_t len)
{
#ifdef DEBUG_LAN
std::cerr << "lan: packet received len=" << len << std::endl;
#endif
// TODO: steering
rxqs[0]->packet_received(data, len);
}
lan_queue_base::lan_queue_base(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
lan_queue_base::lan_queue_base(lan &lanmgr_, const std::string &qtype,
uint32_t &reg_tail_, size_t idx_,
uint32_t &reg_ena_, uint32_t &fpm_basereg_, uint32_t &reg_intqctl_,
uint16_t ctx_size_)
: queue_base(reg_dummy_head, reg_tail_), lanmgr(lanmgr_), enabling(false),
: queue_base(qtype + std::to_string(idx_), reg_dummy_head, reg_tail_),
lanmgr(lanmgr_), enabling(false),
idx(idx_), reg_ena(reg_ena_), fpm_basereg(fpm_basereg_),
reg_intqctl(reg_intqctl_), ctx_size(ctx_size_)
{
......@@ -89,7 +97,9 @@ void lan_queue_base::enable()
if (enabling || enabled)
return;
std::cerr << "lan enabling queue " << idx << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": lan enabling queue " << idx << std::endl;
#endif
enabling = true;
qctx_fetch *qf = new qctx_fetch(*this);
......@@ -105,7 +115,9 @@ void lan_queue_base::enable()
void lan_queue_base::ctx_fetched()
{
std::cerr << "lan ctx fetched " << idx << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": lan ctx fetched " << idx << std::endl;
#endif
initialize();
......@@ -118,7 +130,9 @@ void lan_queue_base::ctx_fetched()
void lan_queue_base::disable()
{
std::cerr << "lan disabling queue " << idx << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": lan disabling queue " << idx << std::endl;
#endif
enabled = false;
// TODO: write back
reg_ena &= ~I40E_QRX_ENA_QENA_STAT_MASK;
......@@ -127,7 +141,9 @@ void lan_queue_base::disable()
void lan_queue_base::interrupt()
{
uint32_t qctl = reg_intqctl;
std::cerr << "lanq: interrupt intctl=" << qctl << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": interrupt intctl=" << qctl << std::endl;
#endif
uint16_t msix_idx = (qctl & I40E_QINT_TQCTL_MSIX_INDX_MASK) >>
I40E_QINT_TQCTL_ITR_INDX_SHIFT;
......@@ -136,7 +152,9 @@ void lan_queue_base::interrupt()
bool cause_ena = !!(qctl & I40E_QINT_TQCTL_CAUSE_ENA_MASK);
if (!cause_ena) {
std::cerr << "lanq: interrupt cause disabled" << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": interrupt cause disabled" << std::endl;
#endif
return;
}
......@@ -146,7 +164,9 @@ void lan_queue_base::interrupt()
}
// TODO throttling?
std::cerr << " setting int0.qidx=" << msix0_idx << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": setting int0.qidx=" << msix0_idx << std::endl;
#endif
lanmgr.dev.regs.pfint_icr0 |= I40E_PFINT_ICR0_INTEVENT_MASK |
(1 << (I40E_PFINT_ICR0_QUEUE_0_SHIFT + msix0_idx));
runner->msi_issue(0);
......@@ -165,7 +185,7 @@ void lan_queue_base::qctx_fetch::done()
lan_queue_rx::lan_queue_rx(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
uint32_t &reg_ena_, uint32_t &reg_fpmbase_, uint32_t &reg_intqctl_)
: lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_,
: lan_queue_base(lanmgr_, "rxq", reg_tail_, idx_, reg_ena_, reg_fpmbase_,
reg_intqctl_, 32)
{
// use larger value for initialization
......@@ -181,7 +201,9 @@ void lan_queue_rx::reset()
void lan_queue_rx::initialize()
{
std::cerr << "lan_queue_rx::initialize()" << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": initialize()" << std::endl;
#endif
uint8_t *ctx_p = reinterpret_cast<uint8_t *>(ctx);
uint16_t *head_p = reinterpret_cast<uint16_t *>(ctx_p + 0);
......@@ -215,10 +237,12 @@ void lan_queue_rx::initialize()
abort();
}
std::cerr << " head=" << reg_dummy_head << " base=" << base <<
#ifdef DEBUG_LAN
std::cerr << qname << ": head=" << reg_dummy_head << " base=" << base <<
" len=" << len << " dbsz=" << dbuff_size << " hbsz=" << hbuff_size <<
" dtype=" << (unsigned) dtype << " longdesc=" << longdesc <<
" crcstrip=" << crc_strip << " rxmax=" << rxmax << std::endl;
#endif
}
queue_base::desc_ctx &lan_queue_rx::desc_ctx_create()
......@@ -229,14 +253,18 @@ queue_base::desc_ctx &lan_queue_rx::desc_ctx_create()
void lan_queue_rx::packet_received(const void *data, size_t pktlen)
{
if (dcache.empty()) {
std::cerr << "rqx: empty, dropping packet" << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": empty, dropping packet" << std::endl;
#endif
return;
}
rx_desc_ctx &ctx = *dcache.front();
std::cerr << "rxq: packet received didx=" << ctx.index << " cnt=" <<
#ifdef DEBUG_LAN
std::cerr << qname << ": packet received didx=" << ctx.index << " cnt=" <<
dcache.size() << std::endl;
#endif
dcache.pop_front();
ctx.packet_received(data, pktlen);
......@@ -276,7 +304,7 @@ void lan_queue_rx::rx_desc_ctx::packet_received(const void *data, size_t pktlen)
lan_queue_tx::lan_queue_tx(lan &lanmgr_, uint32_t &reg_tail_, size_t idx_,
uint32_t &reg_ena_, uint32_t &reg_fpmbase_, uint32_t &reg_intqctl)
: lan_queue_base(lanmgr_, reg_tail_, idx_, reg_ena_, reg_fpmbase_,
: lan_queue_base(lanmgr_, "txq", reg_tail_, idx_, reg_ena_, reg_fpmbase_,
reg_intqctl, 128)
{
desc_len = 16;
......@@ -291,7 +319,9 @@ void lan_queue_tx::reset()
void lan_queue_tx::initialize()
{
std::cerr << "lan_queue_tx::initialize()" << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": initialize()" << std::endl;
#endif
uint8_t *ctx_p = reinterpret_cast<uint8_t *>(ctx);
uint16_t *head_p = reinterpret_cast<uint16_t *>(ctx_p + 0);
......@@ -307,9 +337,11 @@ void lan_queue_tx::initialize()
hwb = !!(*hwb_qlen_p & (1 << 0));
hwb_addr = *hwb_addr_p;
std::cerr << " head=" << reg_dummy_head << " base=" << base <<
#ifdef DEBUG_LAN
std::cerr << qname << ": head=" << reg_dummy_head << " base=" << base <<
" len=" << len << " hwb=" << hwb << " hwb_addr=" << hwb_addr <<
std::endl;
#endif
}
queue_base::desc_ctx &lan_queue_tx::desc_ctx_create()
......@@ -329,7 +361,9 @@ void lan_queue_tx::do_writeback(uint32_t first_idx, uint32_t first_pos,
(first_idx + cnt) % len);
dma->dma_addr = hwb_addr;
std::cerr << "hwb=" << *((uint32_t *) dma->data) << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": hwb=" << *((uint32_t *) dma->data) << std::endl;
#endif
runner->issue_dma(*dma);
}
}
......@@ -348,8 +382,10 @@ bool lan_queue_tx::trigger_tx_packet()
tx_desc_ctx *rd = ready_segments.at(dcnt);
d1 = rd->d->cmd_type_offset_bsz;
std::cerr << "txq: data fetched didx=" << rd->index << " d1=" << d1 <<
std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": data fetched didx=" << rd->index << " d1=" <<
d1 << std::endl;
#endif
uint16_t pkt_len = (d1 & I40E_TXD_QW1_TX_BUF_SZ_MASK) >>
I40E_TXD_QW1_TX_BUF_SZ_SHIFT;
......@@ -365,7 +401,10 @@ bool lan_queue_tx::trigger_tx_packet()
iipt = cmd & (I40E_TX_DESC_CMD_IIPT_MASK);
l4t = (cmd & I40E_TX_DESC_CMD_L4T_EOFT_MASK);
std::cerr << " eop=" << eop << " len=" << pkt_len << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": eop=" << eop << " len=" << pkt_len <<
std::endl;
#endif
total_len += pkt_len;
}
......@@ -386,7 +425,12 @@ bool lan_queue_tx::trigger_tx_packet()
uint16_t tcp_off = maclen + iplen;
xsum_tcp(pktbuf + tcp_off, total_len - tcp_off);
}
std::cerr << " iipt=" << iipt << " l4t=" << l4t << " maclen=" << maclen << " iplen=" << iplen<< std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": iipt=" << iipt << " l4t=" << l4t <<
" maclen=" << maclen << " iplen=" << iplen<< std::endl;
#else
(void) iipt;
#endif
runner->eth_send(pktbuf, total_len);
......@@ -413,14 +457,20 @@ void lan_queue_tx::tx_desc_ctx::prepare()
{
uint64_t d1 = d->cmd_type_offset_bsz;
std::cerr << "txq: desc fetched didx=" << index << " d1=" << d1 << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": desc fetched didx=" << index << " d1=" << d1 <<
std::endl;
#endif
uint8_t dtype = (d1 & I40E_TXD_QW1_DTYPE_MASK) >> I40E_TXD_QW1_DTYPE_SHIFT;
if (dtype == I40E_TX_DESC_DTYPE_DATA) {
uint16_t len = (d1 & I40E_TXD_QW1_TX_BUF_SZ_MASK) >>
I40E_TXD_QW1_TX_BUF_SZ_SHIFT;
std::cerr << " bufaddr=" << d->buffer_addr << " len=" << len << std::endl;
#ifdef DEBUG_LAN
std::cerr << qname << ": bufaddr=" << d->buffer_addr << " len=" <<
len << std::endl;
#endif
data_fetch(d->buffer_addr, len);
} else if (dtype == I40E_TX_DESC_DTYPE_CONTEXT) {
......@@ -533,7 +583,9 @@ lan_queue_tx::dma_hwb::~dma_hwb()
void lan_queue_tx::dma_hwb::done()
{
std::cerr << "txq: tx head written back" << std::endl;
#ifdef DEBUG_LAN
std::cerr << queue.qname << ": tx head written back" << std::endl;
#endif
queue.writeback_done(pos, cnt);
delete this;
}
i40e_bm/i40e_queues.cc
View file @ 2d93957b
......@@ -11,8 +11,9 @@ using namespace i40e;
extern nicbm::Runner *runner;
queue_base::queue_base(uint32_t &reg_head_, uint32_t &reg_tail_)
: active_first_pos(0), active_first_idx(0), active_cnt(0),
queue_base::queue_base(const std::string &qname_, uint32_t &reg_head_,
uint32_t &reg_tail_)
: qname(qname_), active_first_pos(0), active_first_idx(0), active_cnt(0),
base(0), len(0), reg_head(reg_head_), reg_tail(reg_tail_),
enabled(false), desc_len(0)
{
......@@ -45,8 +46,10 @@ void queue_base::trigger_fetch()
if (next_idx + fetch_cnt > len)
fetch_cnt = len - next_idx;
std::cerr << "fetching: avail=" << desc_avail <<
#ifdef DEBUG_QUEUES
std::cerr << qname << ": fetching avail=" << desc_avail <<
" cnt=" << fetch_cnt << " idx=" << next_idx << std::endl;
#endif
// abort if nothign to fetch
if (fetch_cnt == 0)
......@@ -68,7 +71,9 @@ void queue_base::trigger_fetch()
dma->write = false;
dma->dma_addr = base + next_idx * desc_len;
dma->pos = first_pos;
std::cerr << " dma = " << dma << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << qname << ": dma = " << dma << std::endl;
#endif
runner->issue_dma(*dma);
}
......@@ -81,7 +86,7 @@ void queue_base::trigger_process()
uint32_t i;
for (i = 0; i < active_cnt; i++)
if (desc_ctxs[(active_first_pos + i) % MAX_ACTIVE_DESCS]->state
<= desc_ctx::DESC_PROCESSING)
<= desc_ctx::DESC_PREPARED)
break;
// then run all prepared contexts
......@@ -93,6 +98,9 @@ void queue_base::trigger_process()
break;
ctx.state = desc_ctx::DESC_PROCESSING;
#ifdef DEBUG_QUEUES
std::cerr << qname << ": processing desc " << ctx.index << std::endl;
#endif
ctx.process();
}
}
......@@ -113,8 +121,10 @@ void queue_base::trigger_writeback()
if (active_first_pos + cnt > len)
cnt = len - active_first_pos;
std::cerr << "writing back: avail=" << avail << " cnt=" << cnt << " idx=" <<
active_first_idx << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << qname << ": writing back avail=" << avail << " cnt=" << cnt <<
" idx=" << active_first_idx << std::endl;
#endif
if (cnt == 0)
return;
......@@ -130,6 +140,10 @@ void queue_base::trigger_writeback()
void queue_base::reset()
{
#ifdef DEBUG_QUEUES
std::cerr << qname << ": reset" << std::endl;
#endif
enabled = false;
active_first_pos = 0;
active_first_idx = 0;
......@@ -202,9 +216,11 @@ void queue_base::writeback_done(uint32_t first_pos, uint32_t cnt)
ctx.state = desc_ctx::DESC_WRITTEN_BACK;
}
std::cerr << "written back: afi=" << active_first_idx << " afp=" <<
active_first_pos << " acnt=" << active_cnt << " pos=" << first_pos <<
" cnt=" << cnt << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << qname << ": written back afi=" << active_first_idx <<
" afp=" << active_first_pos << " acnt=" << active_cnt << " pos=" <<
first_pos << " cnt=" << cnt << std::endl;
#endif
// then start at the beginning and check how many are written back and then
// free those
......@@ -217,7 +233,9 @@ void queue_base::writeback_done(uint32_t first_pos, uint32_t cnt)
ctx.state = desc_ctx::DESC_EMPTY;
}
std::cerr << " bump_cnt=" << bump_cnt << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << qname << ": bump_cnt=" << bump_cnt << std::endl;
#endif
active_first_pos = (active_first_pos + bump_cnt) % MAX_ACTIVE_DESCS;
active_first_idx = (active_first_idx + bump_cnt) % len;
......@@ -248,6 +266,9 @@ void queue_base::desc_ctx::prepare()
void queue_base::desc_ctx::prepared()
{
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": prepared desc " << index << std::endl;
#endif
assert(state == DESC_PREPARING);
state = DESC_PREPARED;
queue.trigger_process();
......@@ -255,6 +276,9 @@ void queue_base::desc_ctx::prepared()
void queue_base::desc_ctx::processed()
{
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": processed desc " << index << std::endl;
#endif
assert(state == DESC_PROCESSING);
state = DESC_PROCESSED;
queue.trigger_writeback();
......@@ -263,7 +287,9 @@ void queue_base::desc_ctx::processed()
void queue_base::desc_ctx::data_fetch(uint64_t addr, size_t data_len)
{
if (data_capacity < data_len) {
std::cerr << "data_fetch: allocating" << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": data_fetch allocating" << std::endl;
#endif
if (data_capacity != 0)
delete[] ((uint8_t *) data);
......@@ -275,9 +301,12 @@ void queue_base::desc_ctx::data_fetch(uint64_t addr, size_t data_len)
dma->write = false;
dma->dma_addr = addr;
std::cerr << "fetching data idx=" << index << " addr=" << addr << " len=" <<
data_len << std::endl;
std::cerr << "dma = " << dma << " data=" << data << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": fetching data idx=" << index << " addr=" <<
addr << " len=" << data_len << std::endl;
std::cerr << queue.qname << ": dma = " << dma << " data=" << data <<
std::endl;
#endif
runner->issue_dma(*dma);
}
......@@ -290,8 +319,10 @@ void queue_base::desc_ctx::data_fetched(uint64_t addr, size_t len)
void queue_base::desc_ctx::data_write(uint64_t addr, size_t data_len,
const void *buf)
{
std::cerr << "data_write(addr=" << addr << " datalen=" << data_len <<
")" << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": data_write(addr=" << addr << " datalen=" <<
data_len << ")" << std::endl;
#endif
dma_data_wb *data_dma = new dma_data_wb(*this, data_len);
data_dma->write = true;
data_dma->dma_addr = addr;
......@@ -302,8 +333,10 @@ void queue_base::desc_ctx::data_write(uint64_t addr, size_t data_len,
void queue_base::desc_ctx::data_written(uint64_t addr, size_t len)
{
std::cerr << "data_written(addr=" << addr << " datalen=" << len <<
")" << std::endl;
#ifdef DEBUG_QUEUES
std::cerr << queue.qname << ": data_written(addr=" << addr << " datalen=" <<
len << ")" << std::endl;
#endif
processed();
}
......@@ -326,6 +359,10 @@ void queue_base::dma_fetch::done()
desc_ctx &ctx = *queue.desc_ctxs[(pos + i) % queue.MAX_ACTIVE_DESCS];
memcpy(ctx.desc, buf + queue.desc_len * i, queue.desc_len);
#ifdef DEBUG_QUEUES
std::cerr << ctx.queue.qname << ": preparing desc " << ctx.index <<
std::endl;
#endif
ctx.state = desc_ctx::DESC_PREPARING;
ctx.prepare();
}
......
libnicbm/nicbm.cc
View file @ 2d93957b
......@@ -10,7 +10,7 @@
#include <nicbm.h>
#define DEBUG_NICBM 1
//#define DEBUG_NICBM 1
#define SYNC_PERIOD (500 * 1000ULL) // 500ns
#define PCI_LATENCY (500 * 1000ULL) // 500ns
......
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