rem5 run_cmds method

experiments/simbricks/orchestration/instantiation/base.py

@@ -311,6 +311,7 @@ class Instantiation(util_base.IdObj):
                 # both support both we just pick an order
                 insert_dependency(sim_a, depends_on=sim_b)
 
+        # TODO: pre-calculate the socket paths and whether they are listening or connecting sockets in here!
         for sim in self._simulation.all_simulators():
             for comp in sim._components:
                 for sim_inf in comp.interfaces():

experiments/simbricks/orchestration/simulation/base.py

@@ -98,8 +98,13 @@ class Simulator(utils_base.IdObj):
             raise Exception("could not determine eth_latency and sync_period")
         return latency, sync_period, run_sync
 
+    def filter_components_by_pred(
+        self, pred: tp.Callable[[sys_conf.Component], bool]
+    ) -> list[sys_conf.Component]:
+        return list(filter(pred, self._components))
+
     def filter_components_by_type(self, ty) -> list[sys_conf.Component]:
-        return list(filter(lambda comp: isinstance(comp, ty), self._components))
+        return self.filter_components_by_pred(lambda comp: isinstance(comp, ty))
 
     def components(self) -> set[sys_conf.Component]:
         return self._components

experiments/simbricks/orchestration/simulation/host.py

@@ -32,6 +32,8 @@ from simbricks.orchestration.experiment.experiment_environment_new import ExpEnv
 
 if tp.TYPE_CHECKING:
     from simbricks.orchestration.system import host as sys_host
+    from simbricks.orchestration.system import mem as sys_mem
+    from simbricks.orchestration.system import pcie as sys_pcie
 
 
 class HostSim(sim_base.Simulator):
@@ -122,33 +124,42 @@ class Gem5Sim(HostSim):
         if inst.restore_cp():
             cmd += '-r 1 '
 
-        sockets = self._get_sockets(inst=inst) # TODO: FIXME lost info whether this was from a pci device, a mem device or whatever
         latency, sync_period, run_sync = sim_base.Simulator.get_unique_latency_period_sync(channels=self.get_channels())
 
-        pci_devices = self.filter_components_by_type(ty=)
-        # TODO: FIXME get socket by interface!
-        for dev in self.pcidevs:
-            cmd += (
-                f'--simbricks-pci=connect:{env.dev_pci_path(dev)}'
-                f':latency={self.pci_latency}ns'
-                f':sync_interval={self.sync_period}ns'
-            )
-            if  cpu_type == 'TimingSimpleCPU':
-                cmd += ':sync'
-            cmd += ' '
-
-        # TODO: FIXME get socket by interface!
-        for dev in self.memdevs:
-            cmd += (
-                f'--simbricks-mem={dev.size}@{dev.addr}@{dev.as_id}@'
-                f'connect:{env.dev_mem_path(dev)}'
-                f':latency={self.mem_latency}ns'
-                f':sync_interval={self.sync_period}ns'
-            )
-            if cpu_type == 'TimingSimpleCPU':
-                cmd += ':sync'
-            cmd += ' '
+        pci_devices = self.filter_components_by_type(ty=sys_pcie.PCIeSimpleDevice)
+        for dev in pci_devices:
+            for inf in dev.interfaces():
+                socket = self._get_socket(inst=inst, interface=inf)
+                if socket is None:
+                    continue
+                assert socket._type == inst_base.SockType.CONNECT
+                cmd += (
+                    f'--simbricks-pci=connect:{socket._path}'
+                    f':latency={latency}ns'
+                    f':sync_interval={sync_period}ns'
+                )
+                if run_sync:
+                    cmd += ':sync'
+                cmd += ' '
+
+        mem_devices = self.filter_components_by_type(ty=sys_mem.MemSimpleDevice)
+        for dev in mem_devices:
+            for inf in dev.interfaces():
+                socket = self._get_socket(inst=inst, interface=inf)
+                if socket is None:
+                    continue
+                assert socket._type == inst_base.SockType.CONNECT
+                cmd += (
+                    f'--simbricks-mem={dev.size}@{dev.addr}@{dev.as_id}@' # TODO: FIXME
+                    f'connect:{socket._path}'
+                    f':latency={latency}ns'
+                    f':sync_interval={sync_period}ns'
+                )
+                if run_sync:
+                    cmd += ':sync'
+                cmd += ' '
 
+        # TODO: FIXME
         # for net in self.net_directs:
         #     cmd += (
         #         '--simbricks-eth-e1000=listen'

experiments/simbricks/orchestration/system/mem.py

@@ -56,7 +56,7 @@ class MemChannel(base.Channel):
 class MemSimpleDevice(base.Component):
     def __init__(self, s: base.System):
         super().__init__(s)
-        self._mem_if: MemDeviceInterface | None = None
+        self._mem_if: MemDeviceInterface = MemDeviceInterface(c=self)
 
     def interfaces(self) -> list[base.Interface]:
         return [self._mem_if]