{"exp_name": "CdmTCP-gt-cv-switch-6", "metadata": {}, "start_time": 1607494444.329519, "end_time": 1607545187.6091712, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9395978160", " m_axis_ctrl_dma_read_desc_ram_addr = 1664", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 13", " m_axis_ctrl_dma_write_desc_dma_addr = 9515170560", " m_axis_ctrl_dma_write_desc_ram_addr = 864", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 27", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 28", " m_axis_data_dma_write_desc_dma_addr = 8877654016", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 18", " s_axil_rdata = 2147483653", " m_axil_csr_awaddr = 7347372", " m_axil_csr_wdata = 2147483653", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7347372", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259988000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9396716144", " m_axis_ctrl_dma_read_desc_ram_addr = 3840", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 30", " m_axis_ctrl_dma_write_desc_dma_addr = 9516184928", " m_axis_ctrl_dma_write_desc_ram_addr = 416", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 13", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 23", " m_axis_data_dma_write_desc_dma_addr = 8358146048", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 13", " s_axil_rdata = 2147483669", " m_axil_csr_awaddr = 7347884", " m_axil_csr_wdata = 2147483669", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7347884", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259908000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9401058160", " m_axis_ctrl_dma_read_desc_ram_addr = 1920", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 15", " m_axis_ctrl_dma_write_desc_dma_addr = 9515071104", " m_axis_ctrl_dma_write_desc_ram_addr = 192", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 6", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 23", " m_axis_data_dma_write_desc_dma_addr = 8699219968", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 30", " s_axil_rdata = 2147483651", " m_axil_csr_awaddr = 7345260", " m_axil_csr_wdata = 2147483651", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7345260", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259940000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9396337120", " m_axis_ctrl_dma_read_desc_ram_addr = 3712", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 29", " m_axis_ctrl_dma_write_desc_dma_addr = 9515907008", " m_axis_ctrl_dma_write_desc_ram_addr = 64", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 2", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 14", " m_axis_data_dma_write_desc_dma_addr = 8911388672", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 31", " s_axil_rdata = 2147483661", " m_axil_csr_awaddr = 7347628", " m_axil_csr_wdata = 2147483661", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7347628", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259864000"], "stderr": []}, "nic.server.4.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.4.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9410889872", " m_axis_ctrl_dma_read_desc_ram_addr = 1664", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 13", " m_axis_ctrl_dma_write_desc_dma_addr = 9516198720", " m_axis_ctrl_dma_write_desc_ram_addr = 800", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 25", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 1", " m_axis_data_dma_write_desc_dma_addr = 8320233472", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 22", " s_axil_rdata = 2147483670", " m_axil_csr_awaddr = 7340748", " m_axil_csr_wdata = 2147483670", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7340748", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259992000"], "stderr": []}, "nic.server.5.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.5.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9405905088", " m_axis_ctrl_dma_read_desc_ram_addr = 3968", " m_axis_ctrl_dma_read_desc_len = 16", " m_axis_ctrl_dma_read_desc_tag = 31", " m_axis_ctrl_dma_write_desc_dma_addr = 9516319456", " m_axis_ctrl_dma_write_desc_ram_addr = 256", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 8", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 21", " m_axis_data_dma_write_desc_dma_addr = 8637919232", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 5", " s_axil_rdata = 2147483674", " m_axil_csr_awaddr = 7342924", " m_axil_csr_wdata = 2147483674", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 7342924", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259996000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9420930816", " m_axis_ctrl_dma_read_desc_ram_addr = 1792", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 14", " m_axis_ctrl_dma_write_desc_dma_addr = 9516008960", " m_axis_ctrl_dma_write_desc_ram_addr = 992", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 31", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 10", " m_axis_data_dma_write_desc_dma_addr = 8592699392", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 31", " s_axil_rdata = 2147483665", " m_axil_csr_awaddr = 4202028", " m_axil_csr_wdata = 2147483665", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4202028", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259560000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9492564480", " m_axis_ctrl_dma_read_desc_ram_addr = 3968", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 31", " m_axis_ctrl_dma_write_desc_dma_addr = 9516208640", " m_axis_ctrl_dma_write_desc_ram_addr = 192", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 6", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 24", " m_axis_data_dma_write_desc_dma_addr = 8679071744", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 21", " s_axil_rdata = 2147483671", " m_axil_csr_awaddr = 4195052", " m_axil_csr_wdata = 2147483671", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4195052", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259752000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9463664128", " m_axis_ctrl_dma_read_desc_ram_addr = 2048", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 16", " m_axis_ctrl_dma_write_desc_dma_addr = 9516041696", " m_axis_ctrl_dma_write_desc_ram_addr = 128", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 4", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_write_desc_dma_addr = 9229234176", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 21", " s_axil_rdata = 2147483665", " m_axil_csr_awaddr = 4197932", " m_axil_csr_wdata = 2147483665", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4197932", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259764000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9481815616", " m_axis_ctrl_dma_read_desc_ram_addr = 3840", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 30", " m_axis_ctrl_dma_write_desc_dma_addr = 9515011520", " m_axis_ctrl_dma_write_desc_ram_addr = 256", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 8", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 5", " m_axis_data_dma_write_desc_dma_addr = 8466182144", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 2", " s_axil_rdata = 2147483651", " m_axil_csr_awaddr = 4196460", " m_axil_csr_wdata = 2147483651", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4196460", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259756000"], "stderr": []}, "nic.client.4.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.4.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9428673152", " m_axis_ctrl_dma_read_desc_ram_addr = 1792", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_read_desc_tag = 14", " m_axis_ctrl_dma_write_desc_dma_addr = 9516014880", " m_axis_ctrl_dma_write_desc_ram_addr = 128", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 4", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 30", " m_axis_data_dma_write_desc_dma_addr = 9104424960", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 27", " s_axil_rdata = 2147483662", " m_axil_csr_awaddr = 4201932", " m_axil_csr_wdata = 2147483662", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4201932", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259684000"], "stderr": []}, "nic.client.5.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.5.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1 sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", " m_axis_ctrl_dma_read_desc_dma_addr = 9434227520", " m_axis_ctrl_dma_read_desc_len = 64", " m_axis_ctrl_dma_write_desc_dma_addr = 9515840864", " m_axis_ctrl_dma_write_desc_ram_addr = 960", " m_axis_ctrl_dma_write_desc_len = 32", " m_axis_ctrl_dma_write_desc_tag = 30", " m_axis_data_dma_read_desc_ram_addr = 66", " m_axis_data_dma_read_desc_tag = 12", " m_axis_data_dma_write_desc_dma_addr = 8843816960", " m_axis_data_dma_write_desc_len = 66", " m_axis_data_dma_write_desc_tag = 30", " s_axil_rdata = 2147483660", " m_axil_csr_awaddr = 4200844", " m_axil_csr_wdata = 2147483660", " m_axil_csr_wstrb = 15", " m_axil_csr_araddr = 4200844", " ctrl_dma_ram_wr_cmd_ready = 255", " ctrl_dma_ram_rd_cmd_ready = 255", " data_dma_ram_wr_cmd_ready = 255", " data_dma_ram_rd_cmd_ready = 255", " tx_axis_tkeep = 3", " tx_axis_tlast = 1", " rx_axis_tready = 1", "", "", "main_time:19357259108000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.4.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.server.5.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.3.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.4.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.eth.client.5."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62819", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1951033373650", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.870917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.871917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.871917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.871917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.871917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.871917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.871917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.871917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.871917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.871917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.871917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.871917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.872917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.872917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.872917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.872917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.876916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.876916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.876916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.876916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.876916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.876916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.876916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.877916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.877916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.877916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.877916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.877916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.877916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.877916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.101882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.101882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.101882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.101882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.101882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.101882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.101882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.172871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.1 port 5001 connected with 10.0.0.7 port 46836\r", "[ 5] local 10.0.0.1 port 5001 connected with 10.0.0.7 port 46834\r", "[ 5.333239] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.2 sec 832 MBytes 687 Mbits/sec\r", "[ 6] 0.0-10.2 sec 832 MBytes 682 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1951033363650. Starting simulation...", "info: Entering event queue @ 1951033373650. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1951033373973. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62821", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1890299216602", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.866918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.867918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.867918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.867918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.867918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.867918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.867918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.867918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.867918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.868918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.868918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.868918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.872917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.872917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.872917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.872917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.872917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.872917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.872917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.873917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.873917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.873917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.873917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.873917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.873917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.873917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.097883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.097883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.097883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.097883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.097883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.097883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.097883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.166872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.2 port 5001 connected with 10.0.0.8 port 35172\r", "[ 6] local 10.0.0.2 port 5001 connected with 10.0.0.8 port 35174\r", "[ 5.524210] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.1 sec 832 MBytes 688 Mbits/sec\r", "[ 6] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1890299206602. Starting simulation...", "info: Entering event queue @ 1890299216602. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1890299216925. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62822", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2044652844133", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.890916] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.891916] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.891916] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.891916] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.891916] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.891916] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.891916] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.891916] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.891916] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.891916] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.891916] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.892916] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.892916] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.892916] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.892916] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.892916] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.896915] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.896915] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.896915] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.896915] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.896915] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.897915] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.897915] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.897915] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.897915] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.897915] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.897915] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.897915] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.897915] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.897915] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.897915] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.897915] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.897915] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.121881] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.121881] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.121881] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.121881] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.121881] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.121881] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.121881] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.191870] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 6] local 10.0.0.3 port 5001 connected with 10.0.0.9 port 39400\r", "[ 5] local 10.0.0.3 port 5001 connected with 10.0.0.9 port 39398\r", "[ 5.317243] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2044652834133. Starting simulation...", "info: Entering event queue @ 2044652844133. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2044652844456. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62823", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1895724915805", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.865918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.867918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.867918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.867918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.867918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.867918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.867918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.867918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.867918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.867918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.867918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.867918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.873917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.873917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.873917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.873917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.873917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.873917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.873917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.873917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.873917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.873917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.873917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.873917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.873917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.873917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.098883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.098883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.098883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.098883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.098883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.098883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.098883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.167872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.4 port 5001 connected with 10.0.0.10 port 41906\r", "[ 6] local 10.0.0.4 port 5001 connected with 10.0.0.10 port 41908\r", "[ 5.426225] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[ 6] 0.0-10.2 sec 832 MBytes 683 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1895724905805. Starting simulation...", "info: Entering event queue @ 1895724915805. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1895724916128. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.4": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.4", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.4", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.4.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.4.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.4.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62824", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.4 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.4 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.4.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.4. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.4. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1902437514154", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.869917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.871917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.871917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.871917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.871917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.871917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.871917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.871917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.871917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.871917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.871917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.871917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.871917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.871917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.871917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.872917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.877916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.877916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.877916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.877916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.877916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.877916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.877916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.877916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.877916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.877916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.877916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.877916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.877916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.878916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.102882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.102882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.102882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.102882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.102882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.102882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.102882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.172871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.5 port 5001 connected with 10.0.0.11 port 50366\r", "[ 6] local 10.0.0.5 port 5001 connected with 10.0.0.11 port 50364\r", "[ 5.385231] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 6] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 684 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1902437504154. Starting simulation...", "info: Entering event queue @ 1902437514154. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1902437514477. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.5": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.5", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.5", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.5.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.5.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.5.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62825", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.server.5 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.server.5 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.server.5.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.server.5. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.server.5. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1912810307977", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.857919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.858919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.858919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.858919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.858919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.858919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.858919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.858919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.858919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.858919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.858919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.858919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.858919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.859919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.859919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.859919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.863918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.863918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.863918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.863918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.863918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.863918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.863918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.863918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.864918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.864918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.864918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.864918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.864918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.864918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.864918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.864918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.864918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.088884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.088884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.088884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.088884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.088884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.088884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.088884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.157874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.6 port 5001 connected with 10.0.0.12 port 48464\r", "[ 6] local 10.0.0.6 port 5001 connected with 10.0.0.12 port 48466\r", "[ 5.348237] random: crng init done\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0-10.1 sec 832 MBytes 691 Mbits/sec\r", "[ 6] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1912810297977. Starting simulation...", "info: Entering event queue @ 1912810307977. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1912810308300. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62826", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1901330827282", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.875917] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.876917] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.876917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.876917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.876917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.876917] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.876917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.876917] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.876917] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.876917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.876917] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.876917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.876917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.877917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.877917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.877917] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.881916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.881916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.881916] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.881916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.881916] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.881916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.881916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.881916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.881916] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.882916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.882916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.882916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.882916] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.882916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.882916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.882916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.882916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.106882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.106882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.106882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.106882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.106882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.106882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.106882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.177871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.7 port 46836 connected with 10.0.0.1 port 5001\r", "[ 4] local 10.0.0.7 port 46834 connected with 10.0.0.1 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.350237] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.1 sec 832 MBytes 688 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 683 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1901330817282. Starting simulation...", "info: Entering event queue @ 1901330827282. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1901330827605. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62827", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1908306063397", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.868918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.869918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.869918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.869918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.869918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.869918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.869918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.869918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.869918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.869918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.870918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.870918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.870918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.870918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.870918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.870918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.874917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.874917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.874917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.874917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.874917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.875917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.875917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.875917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.875917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.875917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.875917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.875917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.875917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.875917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.875917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.875917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.875917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.099883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.099883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.099883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.099883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.099883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.099883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.099883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.168873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.8 port 35172 connected with 10.0.0.2 port 5001\r", "[ 5] local 10.0.0.8 port 35174 connected with 10.0.0.2 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.424226] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.1 sec 832 MBytes 689 Mbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 9.0-10.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1908306053397. Starting simulation...", "info: Entering event queue @ 1908306063397. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1908306063720. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62828", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1942257972502", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.865919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.866919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.867918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.867918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.867918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.867918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.867918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.867918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.867918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.867918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.867918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.867918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.867918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.872918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.872918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.872918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.872918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.872918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.872918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.872918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.872918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.872918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.872918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.872918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.872918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.097884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.097884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.097884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.168873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.9/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 5] local 10.0.0.9 port 39400 connected with 10.0.0.3 port 5001\r", "[ 4] local 10.0.0.9 port 39398 connected with 10.0.0.3 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.310243] random: crng init done\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 685 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1942257962502. Starting simulation...", "info: Entering event queue @ 1942257972502. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1942257972825. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62829", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1923396351337", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.864919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.865919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.865919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.865919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.865919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.865919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.865919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.865919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.865919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.865919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.865919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.865919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.866919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.866919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.866919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.866919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.870918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.870918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.870918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.870918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.870918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.870918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.871918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.871918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.871918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.871918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.871918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.871918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.871918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.871918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.871918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.095884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.095884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.095884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.095884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.095884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.095884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.095884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.165873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.10/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.10 port 41906 connected with 10.0.0.4 port 5001\r", "[ 5] local 10.0.0.10 port 41908 connected with 10.0.0.4 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.322241] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 686 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 683 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1923396341337. Starting simulation...", "info: Entering event queue @ 1923396351337. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1923396351660. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.4": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.4", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.4", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.4.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.4.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.4.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62830", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.4 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.4 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.4.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.4. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.4. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1914730501195", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.863918] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.864918] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.864918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.864918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.864918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.864918] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.864918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.864918] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.864918] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.864918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.864918] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.864918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.865918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.865918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.865918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.865918] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.869917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.869917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.869917] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.869917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.869917] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.869917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.869917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.870917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.870917] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.870917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.870917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.870917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.870917] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.870917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.870917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.870917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.870917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.094883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.094883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.094883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.094883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.094883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.094883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.094883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.164872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.11/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.5 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.5, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.11 port 50366 connected with 10.0.0.5 port 5001\r", "[ 5] local 10.0.0.11 port 50364 connected with 10.0.0.5 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.297244] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 4] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 0.0-10.1 sec 832 MBytes 690 Mbits/sec\r", "[ 4] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 0.0-10.2 sec 832 MBytes 684 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1914730491195. Starting simulation...", "info: Entering event queue @ 1914730501195. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1914730501518. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.5": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.5", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.5", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.5.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.5.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.5.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System. http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec 3 2020 17:56:02", "gem5 started Dec 9 2020 07:14:05", "gem5 executing on spyder07, pid 62831", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/gem5-out.client.5 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-6/0/gem5-cp.client.5 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/cfg.client.5.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.pci.client.5. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-6/1/nic.shm.client.5. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", " 0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1916331809284", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[ 0.864919] mqnic: loading out-of-tree module taints kernel.\r", "[ 0.866919] mqnic 0000:00:02.0: mqnic probe\r", "[ 0.866919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[ 0.866919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[ 0.866919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[ 0.866919] mqnic 0000:00:02.0: FW version: 0.1\r", "[ 0.866919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[ 0.866919] mqnic 0000:00:02.0: Board version: 0.1\r", "[ 0.866919] mqnic 0000:00:02.0: PHC count: 1\r", "[ 0.866919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[ 0.866919] mqnic 0000:00:02.0: IF count: 1\r", "[ 0.866919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[ 0.866919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[ 0.866919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[ 0.866919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[ 0.866919] mqnic 0000:00:02.0: Creating interface 0\r", "[ 0.872918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[ 0.872918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[ 0.872918] mqnic 0000:00:02.0: Event queue count: 32\r", "[ 0.872918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[ 0.872918] mqnic 0000:00:02.0: TX queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[ 0.872918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[ 0.872918] mqnic 0000:00:02.0: RX queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[ 0.872918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[ 0.872918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[ 0.872918] mqnic 0000:00:02.0: Port count: 1\r", "[ 0.872918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[ 0.872918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[ 0.872918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[ 0.872918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[ 1.097884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[ 1.097884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[ 1.097884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[ 1.097884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[ 1.166873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.12/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.6 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.6, TCP port 5001\r", "TCP window size: 416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[ 4] local 10.0.0.12 port 48464 connected with 10.0.0.6 port 5001\r", "[ 5] local 10.0.0.12 port 48466 connected with 10.0.0.6 port 5001\r", "[ ID] Interval Transfer Bandwidth\r", "[ 4] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 0.0- 1.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 0.0- 1.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5.325241] random: crng init done\r", "[ 4] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 1.0- 2.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 1.0- 2.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 2.0- 3.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 2.0- 3.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 3.0- 4.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 3.0- 4.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 4] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 4.0- 5.0 sec 64.0 MBytes 537 Mbits/sec\r", "[SUM] 4.0- 5.0 sec 128 MBytes 1.07 Gbits/sec\r", "[ 4] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[ 5] 5.0- 6.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 5.0- 6.0 sec 192 MBytes 1.61 Gbits/sec\r", "[ 5] 6.0- 7.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 6.0- 7.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 6.0- 7.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 7.0- 8.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 5] 7.0- 8.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 7.0- 8.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 8.0- 9.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 8.0- 9.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 8.0- 9.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 4] 9.0-10.0 sec 64.0 MBytes 537 Mbits/sec\r", "[ 4] 0.0-10.1 sec 832 MBytes 692 Mbits/sec\r", "[ 5] 9.0-10.0 sec 96.0 MBytes 805 Mbits/sec\r", "[SUM] 9.0-10.0 sec 160 MBytes 1.34 Gbits/sec\r", "[ 5] 0.0-10.2 sec 832 MBytes 687 Mbits/sec\r", "[SUM] 0.0-10.2 sec 1.62 GBytes 1.37 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19357258848849 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB. Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000 pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1916331799284. Starting simulation...", "info: Entering event queue @ 1916331809284. Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1916331809607. Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}
