Commits · f1805db1a671ffb1c99b2eae98e1b1b729fbcc65 · OpenDAS / vllm_cscc

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21 Nov, 2025 1 commit

[Perf] These changes enhance the NUMA functionality of vllm for systems with... · f1805db1

skaraban3807 authored Nov 21, 2025


[Perf] These changes enhance the NUMA functionality of vllm for systems with more than one NUMA nodes per socket (#25559)
Signed-off-by: Siddappa Karabannavar <siddappa.karabannavar@amd.com>

f1805db1

13 Nov, 2025 1 commit
- Add NUMA node validation for CPU thread binding (#28555) · 4ab34f6e
  usberkeley authored Nov 13, 2025
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Signed-off-by: Bradley <bradley.b.pitt@gmail.com>
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  4ab34f6e
11 Jun, 2025 1 commit
- Support no privileged mode on CPU for docker and kubernetes deployments (#19241) · 5c8d34a4
  Louie Tsai authored Jun 11, 2025
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Signed-off-by: Tsai, Louie <louie.tsai@intel.com>
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  5c8d34a4
09 Apr, 2025 1 commit
- [Bugfix] fix gettid method is not define (#16084) · 4e9cf8c1
  rongfu.leng authored Apr 09, 2025
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Signed-off-by: rongfu.leng <rongfu.leng@daocloud.io>
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  4e9cf8c1
02 Apr, 2025 1 commit
- [CPU][Bugfix] Using custom allreduce for CPU backend (#15934) · 550b2801
  Li, Jiang authored Apr 02, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
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  550b2801
08 Jan, 2025 1 commit
- [Hardware][Apple] Native support for macOS Apple Silicon (#11696) · cfd3219f
  Wallas Henrique authored Jan 08, 2025
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Signed-off-by: Wallas Santos <wallashss@ibm.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>
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  cfd3219f
11 Sep, 2024 1 commit
- [Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257) · 0b952af4
  Li, Jiang authored Sep 12, 2024
  
  0b952af4
26 Jul, 2024 1 commit
- [Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend... · 3bbb4936
  Li, Jiang authored Jul 27, 2024
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)
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  3bbb4936