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Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)

Co-authored-by: Varun Sundar Rabindranth <varun@neuralmagic.com>

Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

Signed-off-by: Joe Runde <joe@joerun.de>

Co-authored-by: Chih-Chieh-Yang <7364402+cyang49@users.noreply.github.com>
Co-authored-by: Lucas Wilkinson <lwilkinson@neuralmagic.com>

Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

Signed-off-by: Joe Runde <Joseph.Runde@ibm.com>

Co-authored-by: Michael Goin <michael@neuralmagic.com>
Co-authored-by: youkaichao <youkaichao@gmail.com>
Co-authored-by: zifeitong <zifei.tong@parasail.io>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-neuralmagic@users.noreply.github.com>

Inspired by #5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.

Co-authored-by: Varun Sundar Rabindranath <varunsundar08@gmail.com>
Co-authored-by: Varun Sundar Rabindranath <varun@neuralmagic.com>

Co-authored-by: Cody Yu <hao.yu.cody@gmail.com>