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Signed-off-by: npanpaliya <nishidha.panpaliya@partner.ibm.com>

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Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
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Co-authored-by: Sungjae Lee <33976427+llsj14@users.noreply.github.com>
Co-authored-by: shaochangxu <85155497+shaochangxu@users.noreply.github.com>
Co-authored-by: shaochangxu.scx <shaochangxu.scx@antgroup.com>
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Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
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Co-authored-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
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Co-authored-by: Rui Qiao <161574667+ruisearch42@users.noreply.github.com>
Co-authored-by: Roger Wang <ywang@roblox.com>

Signed-off-by: Wallas Santos <wallashss@ibm.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: mgoin <michael@neuralmagic.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: Thomas Parnell <tpa@zurich.ibm.com>

[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)

Co-authored-by: Jianan Gu <jianan.gu@intel.com>

Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Yuan Zhou <yuan.zhou@intel.com>