Commits · b639327ad94b3aa16022ebea49f8e525660b736b · OpenDAS / vllm_cscc · GitLab

"tests/vscode:/vscode.git/clone" did not exist on "9608844f96e0e739bead72520b7710f1b6f82b65"

11 Jul, 2025 1 commit

[Core] Add Flashinfer TRTLLM Backend for Flashinfer decode path (SM100). (#19825) · 7bd4c37a

Pavani Majety authored Jul 11, 2025


Signed-off-by: Pavani Majety <pmajety@nvidia.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: shuw <shuw@nvidia.com>
Co-authored-by: mgoin <mgoin64@gmail.com>

7bd4c37a

10 Jul, 2025 3 commits
- [ROCm][Regression] Remove tensor creation that harms performance on ROCm (#20741) · 5b8366b6
  Gregory Shtrasberg authored Jul 10, 2025
```
Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
```
  5b8366b6
- [Doc] Add engine args back in to the docs (#20674) · 3482fd7e
  Harry Mellor authored Jul 10, 2025
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Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
```
  3482fd7e
- [BugFix] Fix `VllmConfig()` construction on all platforms (#20695) · ffbcc9e7
  Nick Hill authored Jul 10, 2025
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Signed-off-by: Nick Hill <nhill@redhat.com>
```
  ffbcc9e7
09 Jul, 2025 3 commits

[XPU][CI] enhance xpu test support (#20652) · a3e4e85e

Liangliang Ma authored Jul 10, 2025


Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>
Co-authored-by: zhenwei-intel <zhenweiliu@habana.ai>

a3e4e85e

[Hardware][PPC64LE] Enable V1 for ppc64le and ARM (#20554) · 6db31e7a

Akash kaothalkar authored Jul 09, 2025


Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Nikhil Gupta <nikhil.gupta2@arm.com>

6db31e7a

[misc]refactor `Platform.set_device` method (#20262) · 0b407479
Kunshang Ji authored Jul 09, 2025
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Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
```
0b407479

08 Jul, 2025 1 commit
- [xpu]feat: support multi-lora on xpu (#20616) · a4c23314
  Yan Ma authored Jul 08, 2025
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Signed-off-by: yan <yan.ma@intel.com>
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  a4c23314
07 Jul, 2025 3 commits

[XPU] log clean up for XPU platform (#20553) · 3112271f
Yan Ma authored Jul 07, 2025
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Signed-off-by: yan <yan.ma@intel.com>
```
3112271f
[XPU][CI] add v1/core test in xpu hardware ci (#20537) · 2c5ebec0
Liangliang Ma authored Jul 07, 2025
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Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>
```
2c5ebec0

[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl... · 6e2c19ce

Yang Yang authored Jul 07, 2025


[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)
Signed-off-by: dbyoung18 <yang5.yang@intel.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

6e2c19ce

06 Jul, 2025 2 commits

[V1] Support any head size for FlexAttention backend (#20467) · 9fb52e52
Cyrus Leung authored Jul 07, 2025
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Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
```
9fb52e52

[V0 deprecation] Remove V0 CPU/XPU/TPU backends (#20412) · e202dd27

Woosuk Kwon authored Jul 06, 2025


Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

e202dd27

05 Jul, 2025 1 commit
- [v1] Re-add fp32 support to v1 engine through FlexAttention (#19754) · 32c9be22
  Isotr0py authored Jul 05, 2025
```
Signed-off-by: Isotr0py <2037008807@qq.com>
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
```
  32c9be22
04 Jul, 2025 1 commit
- [Platform] Add custom default max tokens (#18557) · a4113b03
  Gabriel Marinho authored Jul 03, 2025
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Signed-off-by: Gabriel Marinho <gmarinho@ibm.com>
```
  a4113b03
02 Jul, 2025 1 commit
- [UT][intel GPU] use current_platform instead of device hardcode in v1 tests (#20169) · a0389e05
  Liangliang Ma authored Jul 02, 2025
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Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>
```
  a0389e05
01 Jul, 2025 2 commits
- [BugFix][V1][ROCm] Triton MLA uses V0 backend on V1 engine (#19067) · 96453cfa
  TY-AMD authored Jul 01, 2025
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Signed-off-by: Tianyuan Wu <Tianyuan.Wu@amd.com>
```
  96453cfa
- [CPU] Update custom ops for the CPU backend (#20255) · 6cc1e7d9
  Li, Jiang authored Jul 01, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
```
  6cc1e7d9
26 Jun, 2025 2 commits
- [Hardware][Intel GPU] Add v1 Intel GPU support with Flash attention backend. (#19560) · b69781f1
  Kunshang Ji authored Jun 27, 2025
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Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
```
  b69781f1
- [Bugfix] Allow `CUDA_VISIBLE_DEVICES=''` in `Platform.device_id_to_physical_device_id` (#18979) · 65397e40
  Seiji Eicher authored Jun 26, 2025
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Signed-off-by: Seiji Eicher <seiji@anyscale.com>
```
  65397e40
25 Jun, 2025 1 commit
- [TPU] Add TPU specific var VLLM_TPU_MOST_MODEL_LEN (#19919) · 2d7620c3
  Chenyaaang authored Jun 25, 2025
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Signed-off-by: Chenyaaang <chenyangli@google.com>
```
  2d7620c3
20 Jun, 2025 1 commit
- [Bugfix][Ray] Set the cuda context eagerly in the ray worker (#19583) · 5e666f72
  kourosh hakhamaneshi authored Jun 19, 2025
  
  5e666f72
19 Jun, 2025 1 commit
- Fix FA2 fallback for Blackwell V1 (#19781) · 36239f79
  Michael Goin authored Jun 19, 2025
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Signed-off-by: mgoin <mgoin64@gmail.com>
```
  36239f79
18 Jun, 2025 2 commits

[Hardware][AMD] integrate aiter chunked prefill into vllm (#18596) · 8b6e1d63

Zzz9990 authored Jun 18, 2025


Signed-off-by: fsx950223 <fsx950223@outlook.com>
Signed-off-by: charlifu <charlifu@amd.com>
Co-authored-by: fsx950223 <fsx950223@outlook.com>
Co-authored-by: charlifu <charlifu@amd.com>

8b6e1d63

[Platform] Allow platform use V1 Engine by default (#19792) · 257ab954
wangxiyuan authored Jun 18, 2025
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Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>
```
257ab954

17 Jun, 2025 1 commit
- [Feature][ROCm] Add full graph capture support for TritonAttentionBackend (#19158) · a44b1c95
  Charlie Fu authored Jun 17, 2025
```
Signed-off-by: charlifu <charlifu@amd.com>
```
  a44b1c95
16 Jun, 2025 1 commit
- [Misc] Remove duplicate multiproc method setting for CPU platform (#19649) · a5e7242d
  Isotr0py authored Jun 16, 2025
```
Signed-off-by: Isotr0py <2037008807@qq.com>
```
  a5e7242d
13 Jun, 2025 1 commit
- [CPU] Refine default config for the CPU backend (#19539) · 64587211
  Li, Jiang authored Jun 13, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
```
  64587211
12 Jun, 2025 1 commit
- [Bugfix][V1] Allow manual FlashAttention for Blackwell (#19492) · af09b3f0
  Michael Goin authored Jun 12, 2025
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Signed-off-by: mgoin <mgoin64@gmail.com>
```
  af09b3f0
11 Jun, 2025 1 commit
- Add cache to cuda get_device_capability (#19436) · 7484e1fc
  Michael Goin authored Jun 11, 2025
```
Signed-off-by: mgoin <mgoin64@gmail.com>
```
  7484e1fc
10 Jun, 2025 2 commits
- Revert "[v1] Add fp32 support to v1 engine through flex attn" (#19404) · 5f1ac1e1
  Isotr0py authored Jun 10, 2025
  
  5f1ac1e1
- Automatically bind CPU OMP Threads of a rank to CPU ids of a NUMA node. (#17930) · 9368cc90
  Louie Tsai authored Jun 09, 2025
```
Signed-off-by: Tsai, Louie <louie.tsai@intel.com>
Co-authored-by: Li, Jiang <bigpyj64@gmail.com>
```
  9368cc90
09 Jun, 2025 1 commit
- [v1] Add fp32 support to v1 engine through flex attn (#19319) · b8089195
  Isotr0py authored Jun 09, 2025
```
Signed-off-by: Isotr0py <2037008807@qq.com>
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
```
  b8089195
07 Jun, 2025 1 commit
- Add FlexAttention to V1 (#16078) · cf02f9b2
  Driss Guessous authored Jun 07, 2025
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Signed-off-by: drisspg <drisspguessous@gmail.com>
```
  cf02f9b2
06 Jun, 2025 1 commit
- [Bugfix] Fix EAGLE vocab embedding construction for Llama 70B (#19033) · 3465b87e
  Benjamin Chislett authored Jun 05, 2025
```
Signed-off-by: Benjamin Chislett <benjamin.chislett@centml.ai>
```
  3465b87e
05 Jun, 2025 2 commits
- [V1] Use FlashInfer by default on Blackwell GPUs (#19118) · 87360308
  Michael Goin authored Jun 05, 2025
  
  87360308
- [P/D][NixlConnector] Enable FlashInfer backend (#19090) · 9ef9173c
  Nicolò Lucchesi authored Jun 05, 2025
  
  9ef9173c
04 Jun, 2025 3 commits
- [Bugfix] fix v1 cpu worker fails on macOS (#19121) · ef3f98b5
  Kebe authored Jun 05, 2025
  
  ef3f98b5
- [NVIDIA] Add Cutlass MLA backend (#17625) · 41aa5784
  Kaixi Hou authored Jun 04, 2025
  
  41aa5784
- [CPU] V1 support for the CPU backend (#16441) · 4555143e
  Li, Jiang authored Jun 04, 2025
  
  4555143e