Commits · a6760f6456b714409685e23301c820a85da856ca · OpenDAS / vllm_cscc

26 Nov, 2024 1 commit

[Feature] vLLM ARM Enablement for AARCH64 CPUs (#9228) · a6760f64

Sanket Kale authored Nov 26, 2024


Signed-off-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: mgoin <michael@neuralmagic.com>

a6760f64

19 Nov, 2024 1 commit

Fix: Build error seen on Power Architecture (#10421) · 1ea291a4

Manjul Mohan authored Nov 19, 2024


Signed-off-by: Manjul Mohan <manjul.mohan@ibm.com>
Signed-off-by: B-201 <Joy25810@foxmail.com>
Signed-off-by: Isotr0py <2037008807@qq.com>
Signed-off-by: youkaichao <youkaichao@gmail.com>
Signed-off-by: ismael-dm <ismaeldm99@gmail.com>
Signed-off-by: Andrew Nesbitt <andrewnez@gmail.com>
Signed-off-by: mgoin <michael@neuralmagic.com>
Signed-off-by: yan ma <yan.ma@intel.com>
Signed-off-by: Angus Wang <wangjadehao@gmail.com>
Signed-off-by: Lucas Wilkinson <lwilkinson@neuralmagic.com>
Signed-off-by: rickyx <rickyx@anyscale.com>
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: Mengqing Cao <cmq0113@163.com>
Signed-off-by: Travis Johnson <tsjohnso@us.ibm.com>
Co-authored-by: Manjul Mohan manjul.mohan@ibm.com <manjulmohan@ltcd97-lp2.aus.stglabs.ibm.com>
Co-authored-by: B-201 <Joy25810@foxmail.com>
Co-authored-by: Isotr0py <2037008807@qq.com>
Co-authored-by: youkaichao <youkaichao@gmail.com>
Co-authored-by: ismael-dm <ismaeldm99@gmail.com>
Co-authored-by: Andrew Nesbitt <andrewnez@gmail.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>
Co-authored-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Angus Wang <wangjadehao@gmail.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: Ricky Xu <rickyx@anyscale.com>
Co-authored-by: Kevin H. Luu <kevin@anyscale.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
Co-authored-by: Mengqing Cao <cmq0113@163.com>
Co-authored-by: Travis Johnson <tsjohnso@us.ibm.com>
Co-authored-by: Russell Bryant <rbryant@redhat.com>

1ea291a4

07 Nov, 2024 2 commits
- [Hardware][CPU][bugfix] Fix half dtype support on AVX2-only target (#10108) · a6f332d0
  Li, Jiang authored Nov 07, 2024
```
Signed-off-by: jiang1.li <jiang1.li@intel.com>
```
  a6f332d0
- [Hardware][CPU] Update torch 2.5 (#9911) · a4b3e0c1
  Li, Jiang authored Nov 07, 2024
```
Signed-off-by: jiang1.li <jiang1.li@intel.com>
```
  a4b3e0c1
17 Oct, 2024 1 commit
- [Hardware][CPU] compressed-tensor INT8 W8A8 AZP support (#9344) · 5eda21e7
  Li, Jiang authored Oct 18, 2024
  
  5eda21e7
04 Oct, 2024 1 commit
- [Hardware][PowerPC] Make oneDNN dependency optional for Power (#9039) · e5dc713c
  Varad Ahirwadkar authored Oct 04, 2024
```
Signed-off-by: Varad Ahirwadkar <varad.ahirwadkar1@ibm.com>
```
  e5dc713c
23 Sep, 2024 1 commit
- [Bugfix] Fix CPU CMake build (#8723) · 57a0702e
  Luka Govedič authored Sep 22, 2024
```
Co-authored-by: Yuan <yuan.zhou@intel.com>
```
  57a0702e
11 Sep, 2024 1 commit
- [Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257) · 0b952af4
  Li, Jiang authored Sep 12, 2024
  
  0b952af4
02 Aug, 2024 1 commit
- [Misc] Disambiguate quantized types via a new ScalarType (#6396) · a8d604ca
  Lucas Wilkinson authored Aug 02, 2024
  
  a8d604ca
26 Jul, 2024 1 commit
- [Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend... · 3bbb4936
  Li, Jiang authored Jul 27, 2024
```
[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)
```
  3bbb4936
26 Jun, 2024 1 commit
- Support CPU inference with VSX PowerPC ISA (#5652) · 38a1674a
  Chip Kerchner authored Jun 26, 2024
  
  38a1674a
17 Jun, 2024 1 commit
- [CI/BUILD] Support non-AVX512 vLLM building and testing (#5574) · ab66536d
  Jie Fu (傅杰) authored Jun 18, 2024
  
  ab66536d
13 Jun, 2024 1 commit
- [Hardware][Intel] Support CPU inference with AVX2 ISA (#5452) · cd9c0d65
  Jie Fu (傅杰) authored Jun 14, 2024
  
  cd9c0d65
09 Jun, 2024 1 commit
- [Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047) · 5467ac31
  bnellnm authored Jun 09, 2024
  
  5467ac31
02 Apr, 2024 1 commit

[Hardware][Intel] Add CPU inference backend (#3634) · 0e3f06fe

bigPYJ1151 authored Apr 02, 2024


Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Yuan Zhou <yuan.zhou@intel.com>

0e3f06fe