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区分pcie和hglink custom allreduce的使用
vllm：export VLLM_CUSTOM_CACHE=1
dtk：export HIP_KERNEL_EVENT_SYSTENFENCE=1

set VLLM_USE_FUSED_RMS_ROPE=1
add SUPPORT_MOE_MARLIN_W16A16 to use moe marlin on bw
support fa kvcache fp8 (todo: add VLLM_USE_QUERY_QUANT to not use q quant)
update moe_align_block_size

fix _forward_encoder_attention
remove medusa
set VLLM_PCIE_USE_CUSTOM_ALLREDUCE=1

[gpt-oss-120b] MoE configs for BW1000 TP=8

实现了用于优化张量计算的 rms_mrope_fuse 和 rms_mrope_fuse_fake 方法
更新了 forward：在满足条件时走新的 M-RoPE 融合路径
增强了 Qwen3MoeModel 对动态参数维度的支持，以适配该功能

update weights_not_loaded and flash_mla_with_kvcache
update paged_mqa_logits