Commits · 56e544f24b62d647ba05cccf51756c2ebebae66f · OpenDAS / vllm_cscc

10 Jul, 2025 1 commit
- [Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129) · c7753a98
  nishith-fujitsu authored Jul 10, 2025
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Signed-off-by: nishith-fujitsu <nishith.jaiswal@fujitsu.com>
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  c7753a98
01 Jul, 2025 1 commit
- [CPU] Update custom ops for the CPU backend (#20255) · 6cc1e7d9
  Li, Jiang authored Jul 01, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
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  6cc1e7d9
26 Jun, 2025 1 commit
- [CPU] Fix torch version in x86 CPU backend (#19258) · 0567c824
  Li, Jiang authored Jun 26, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
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  0567c824
08 May, 2025 1 commit

[Hardware][Power] Enable compressed tensor W8A8 INT8 quantization for POWER (#17153) · e515668e

Akash kaothalkar authored May 08, 2025


Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: mgoin <mgoin64@gmail.com>

e515668e

07 May, 2025 1 commit
- Make key optional for rotary embedding (#17566) · 98c89e16
  Yong Hoon Shin authored May 07, 2025
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Signed-off-by: Yong Hoon Shin <yhshin@meta.com>
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  98c89e16
02 Apr, 2025 1 commit
- [CPU][Bugfix] Using custom allreduce for CPU backend (#15934) · 550b2801
  Li, Jiang authored Apr 02, 2025
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Signed-off-by: jiang1.li <jiang1.li@intel.com>
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  550b2801
25 Mar, 2025 1 commit
- [Kernel][CPU] CPU MLA (#14744) · 4f044b1d
  Thien Tran authored Mar 25, 2025
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Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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  4f044b1d
23 Jan, 2025 1 commit

[FP8][Kernel] Dynamic kv cache scaling factors computation (#11906) · e97f802b

Gregory Shtrasberg authored Jan 23, 2025


Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
Co-authored-by: Micah Williamson <micah.williamson@amd.com>

e97f802b

05 Jan, 2025 1 commit
- [MISC] Replace c10::optional with std::optional (#11730) · 4068f4b5
  Lu Fang authored Jan 04, 2025
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Signed-off-by: Lu Fang <lufang@fb.com>
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  4068f4b5
17 Oct, 2024 1 commit
- [Hardware][CPU] compressed-tensor INT8 W8A8 AZP support (#9344) · 5eda21e7
  Li, Jiang authored Oct 18, 2024
  
  5eda21e7
16 Sep, 2024 1 commit
- [Kernel] AQ AZP 3/4: Asymmetric quantization kernels (#7270) · 5d73ae49
  Luka Govedič authored Sep 16, 2024
  
  5d73ae49
11 Sep, 2024 2 commits
- [Kernel][Misc] register ops to prevent graph breaks (#6917) · 73202dbe
  bnellnm authored Sep 11, 2024
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Co-authored-by: Sage Moore <sage@neuralmagic.com>
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  73202dbe
- [Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257) · 0b952af4
  Li, Jiang authored Sep 12, 2024
  
  0b952af4
02 Aug, 2024 1 commit
- [Misc] Disambiguate quantized types via a new ScalarType (#6396) · a8d604ca
  Lucas Wilkinson authored Aug 02, 2024
  
  a8d604ca
26 Jul, 2024 1 commit
- [Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend... · 3bbb4936
  Li, Jiang authored Jul 27, 2024
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation  (#6125)
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  3bbb4936
16 Jul, 2024 1 commit
- [Kernel][Attention] Separate `Attention.kv_scale` into `k_scale` and `v_scale` (#6081) · 978aed53
  Michael Goin authored Jul 16, 2024
  
  978aed53
21 Jun, 2024 1 commit
- [Kernel][CPU] Add Quick `gelu` to CPU (#5717) · bd620b01
  Roger Wang authored Jun 20, 2024
  
  bd620b01
09 Jun, 2024 1 commit
- [Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047) · 5467ac31
  bnellnm authored Jun 09, 2024
  
  5467ac31