GitLab

feat(v1 attention): 为 ROCm FlashAttention 接入 unified kv layout，并打通 mm_prefix、qq_bias 与 use_alibi_sqrt 透传
在 ROCm FlashAttention 后端增加 unified KV layout 选择逻辑
接入 unified varlen kernel 调用路径
在 FlashAttention metadata 中补充 mm_prefix_range 与 qq_bias 透传

Signed-off-by: Paco Xu <paco.xu@daocloud.io>

Signed-off-by: mohammad najafi <mohammad.najafi@amd.com>

Signed-off-by: yewentao256 <zhyanwentao@126.com>

Signed-off-by: marksverdhei <marksverdhei@hotmail.com>
Signed-off-by: Markus / Mark <46672778+marksverdhei@users.noreply.github.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
Co-authored-by: mgoin <mgoin64@gmail.com>

Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>

Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com>

Signed-off-by: Alex Sun <alex.s@amd.com>

Signed-off-by: yewentao256 <zhyanwentao@126.com>

Signed-off-by: ganyi <ygan@amd.com>

[Attention][MLA] Make FLASHINFER_MLA the default MLA backend on Blackwell, and TRTLLM the default prefill (#32615)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>

Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>

区分pcie和hglink custom allreduce的使用
vllm：export VLLM_CUSTOM_CACHE=1
dtk：export HIP_KERNEL_EVENT_SYSTENFENCE=1

set VLLM_USE_FUSED_RMS_ROPE=1
add SUPPORT_MOE_MARLIN_W16A16 to use moe marlin on bw
support fa kvcache fp8 (todo: add VLLM_USE_QUERY_QUANT to not use q quant)
update moe_align_block_size

fix _forward_encoder_attention
remove medusa
set VLLM_PCIE_USE_CUSTOM_ALLREDUCE=1

[Attention][MLA] Make `FLASHINFER_MLA` the default MLA backend on Blackwell, and TRTLLM the default prefill (#32339)
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>

Signed-off-by: shen-shanshan <467638484@qq.com>

Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>

Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com>

Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>

Signed-off-by: Andy Xie <andy.xning@gmail.com>

Signed-off-by: sihao.li <sihao.li@intel.com>

Signed-off-by: Wei-Yu Lin <weiyulin@google.com>
Signed-off-by: weiyu <62784299+weiyu0824@users.noreply.github.com>

Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>

Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>

Signed-off-by: zzzzwwjj <1183291235@qq.com>
Signed-off-by: zzzzwwjj <34335947+zzzzwwjj@users.noreply.github.com>
Co-authored-by: Cyrus Leung <cyrus.tl.leung@gmail.com>

Signed-off-by: wangxiyuan <wangxiyuan1007@gmail.com>

Signed-off-by: SameerAsal <SameerAsal@users.noreply.github.com>
Co-authored-by: SameerAsal <SameerAsal@users.noreply.github.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

[ROCm][Bugfix] Fix accuracy issue on fmoe when `VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS` enabled (#31523)
Signed-off-by: ganyi <ygan@amd.com>

Signed-off-by: sihao.li <sihao.li@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>

[XPU] decrease IGC_ForceOCLSIMDWidth for speculative decoding triton-xpu kernel compilation (#30538)
Signed-off-by: Yan Ma <yan.ma@intel.com>

Signed-off-by: c0de128 <kevin.mckay@outlook.com>
Co-authored-by: Claude Sonnet 4.5 <noreply@anthropic.com>