vllm/worker/hpu_model_runner.py · 56a735261c17d04529bca08d8245b1d383bae5f0 · OpenDAS / vllm_cscc

[INTEL-HPU][v0] Port delayed sampling to upstream (#16949) · 56a73526

Chendi.Xue authored Apr 22, 2025


Signed-off-by: Michal Adamczyk <michal.adamczyk@intel.com>
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
Co-authored-by: Michal Adamczyk <madamczyk@habana.ai>

56a73526

hpu_model_runner.py 106 KB

Replace hpu_model_runner.py