• Yu Cheng's avatar
    [Refactor] Enhance layout inference logic in ParallelOp (#420) · bf27e641
    Yu Cheng authored
    * Updated the layout inference in ParallelOp to improve the selection of source buffers for layout accuracy.
    * Introduced logic to choose the read source buffer based on the number of indices, ensuring more precise layout inference.
    * Refactored the loop handling to maintain clarity and improve the overall robustness of the layout inference process.
    bf27e641
parallel.cc 11.3 KB