Commits · bd55e7ba5f0235a80eaa63d49adaa8fb7c6ced50 · OpenDAS / TransformerEngine

29 Sep, 2025 1 commit

[Core][PyTorch] NVFP4 recipe (#2177) · 3f5b4754

Kirthi Shankar Sivamani authored Sep 29, 2025



* Add NVFP4 recipe
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>
Co-authored-by: Frank Sun <frsun@nvidia.com>
Co-authored-by: Oleg Goncharov <ogoncharov@nvidia.com>
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* Add MathDx dependency to GitHub builds
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* Suggestions from GitHub Copilot
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* Move 2x shape logic from core to PyTorch
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* Fix compilation errors with CUDA 12.1
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* SM 70 is not supported in CUDA 13
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* Typo
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* Revert "Move 2x shape logic from core to PyTorch"

This reverts commit f8b2a2d0111d9af690b43bb98ae448d9a430a185.
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* Added dequantize kernel for FP4
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* Fix linter warning
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* Add NVFP4 support with fusible ops

Use logical tensor dims for PyTorch NVFP4 tensors. Temporarily add unfused dequantize impl. Fix bug where NVFP4 recipe was not configurable.
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* Fix logic for 2x shapes and move to PyTorch
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* Fix CG test model config
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* Debug NVFP4 tensor size function
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* Proper handling of the RNG state
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* Test SR properly
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* Fix workspace size for GEMM heuristic.
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* Fix compile error in C++ NVFP4 test

Some some numeric errors when blocks are all zero.
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* fix distrbuted test problem shape
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* proper assert dim for low precision AG TP
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* clean up duplicated code in nvfp4_utils.cuh
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* lint
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* pylint: disable=unused-argument
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* `nvte_cublas_gemm_v2` to take alpha pointer (#12)

* make nvte_cublas_gemm_v2 to take alpha/beta pointers
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* users are expected to pass a valid C_tensor
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* typos
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* API to have const float* alpha
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* Minor tweaks

Support arbitrary beta scales. Increase workspace to be aligned to 128 bytes.
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* Debug IMA with alpha pointer
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* Support fused amax kernels with NVFP4 quantization
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* Disable fused amax with cuDNN LayerNorm kernel
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* Add NVFP4 cases to distributed tests for TE ops
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* Change assert to NVTE_CHECK in the hadamard cast fusion
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* Fix compile error
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* Use global thread IDs for Philox subsequences
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* Add shape checks for NVFP4 cast kernels
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* Do not fuse amax if cuDNN normalization is forced by envvar
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3f5b4754

29 Aug, 2025 1 commit

[Common] Add checks to CUDA kernel launch and CUDA API calls (#2074) · 4285874d

Xin Yao authored Aug 29, 2025



* add checks to cuda kernel launch and cuda API calls
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* Remove exceptions from destructors
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* fix weired dispatch in ln/rmsnorm
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4285874d

14 Aug, 2025 1 commit

[Core] Add launch bounds to swizzle kernels (#2076) · 12065ac2

Kirthi Shankar Sivamani authored Aug 14, 2025



Add launch bounds to swizzle kernel, use empty scale inv
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

12065ac2

06 Aug, 2025 1 commit

[PyTorch] Multi-tensor swizzle scaling factors for MXFP8 and fuse padding zeros (#2019) · c0d2f1a5

Xin Yao authored Aug 07, 2025



* for loop
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* bulk alloc
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* multi-tensor swizzle
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* pad zeros in swizzle kernels
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* unify single- and multi-tensor swizzle
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* fix empty tensor list
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* fix bug for col swizzle
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* check context & fix signifiers
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Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

c0d2f1a5

29 May, 2025 1 commit

Avoid memory allocations and deallocations when creating NVTETensor (#1813) · 4292653c

Przemyslaw Tredak authored May 29, 2025



* Changed the Tensor allocation strategy
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>

* Fixes
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* Disable debug flag
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* Fix the double free error
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* Fix
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* Fixed pyTorch recipe extension
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* Fix
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* Fix
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* Hide TensorAllocator and fix the usage in LayerNorm
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* Cleaning
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* Fix
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* Fix permutation
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Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

4292653c

07 Feb, 2025 1 commit
- Update main branch with TE 2.0 code, update version to 2.1.0.dev0 · 544dd14b
  Przemek Tredak authored Feb 07, 2025
```
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
```
  544dd14b