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* pipeclean, fix nvfp4 padding of 32 alignment
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>

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* numerical test passed
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* fix CI failure with test_cast_master_weights_to_fp8 (in a hacky way)
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* found CUDA mis-aligned address error in training in multi-swizzle, hack the vec_load_size to 1 to unblock
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* leave comments about alignment issue
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* fused bulk alloc nvfp4
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* fix RHT sign mask CPU overhead
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* fix
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* resolve comments
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* Remove incorrect logic that treats 0-D tensor as uninitialized

Tensor shape logic still requires treating 0-D tensor as uninitialized.
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* Fix invalid conversion from tensor to int
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* Update to_string(NVTEScalingMode) to include block scaling
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* Add `nvte_swizzle_block_scaling_to_mxfp8_scaling_factors`
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* Convert FP8 block scaling tensors to MXFP8 tensors on Blackwell and newer in GEMM
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* Allow Blackwell and newer in Deepseek recipe compatbility check
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* Allow data_rows % 4 != 0 in 1d kernel
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* Load scaling factors in unswizzled order in 1d kernel
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* Enforce use of power of two scaling
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* Skip the FP8 block scaling exact GEMM test on Blackwell
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* Skip further tests with pow_2_scales=False
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* Initial implementation of tensor conversion for grouped gemm
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* Skip non power of two scaling cpp unit tests
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* Fix handling of all gather
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* Apply suggestions from code review
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* Use compute capability 10.0 for logic with Blackwell
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* Apply suggestions from code review
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* Add NVFP4 recipe
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* Add MathDx dependency to GitHub builds
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* Suggestions from GitHub Copilot
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* Move 2x shape logic from core to PyTorch
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* Fix compilation errors with CUDA 12.1
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* SM 70 is not supported in CUDA 13
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* Typo
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* Revert "Move 2x shape logic from core to PyTorch"

This reverts commit f8b2a2d0111d9af690b43bb98ae448d9a430a185.
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* Added dequantize kernel for FP4
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* Fix linter warning
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* Add NVFP4 support with fusible ops

Use logical tensor dims for PyTorch NVFP4 tensors. Temporarily add unfused dequantize impl. Fix bug where NVFP4 recipe was not configurable.
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* Fix logic for 2x shapes and move to PyTorch
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* Fix CG test model config
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* Debug NVFP4 tensor size function
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* Proper handling of the RNG state
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* Test SR properly
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* Fix workspace size for GEMM heuristic.
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* Fix compile error in C++ NVFP4 test

Some some numeric errors when blocks are all zero.
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* fix distrbuted test problem shape
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* proper assert dim for low precision AG TP
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* clean up duplicated code in nvfp4_utils.cuh
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* lint
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* pylint: disable=unused-argument
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* `nvte_cublas_gemm_v2` to take alpha pointer (#12)

* make nvte_cublas_gemm_v2 to take alpha/beta pointers
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* users are expected to pass a valid C_tensor
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* typos
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* API to have const float* alpha
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* Minor tweaks

Support arbitrary beta scales. Increase workspace to be aligned to 128 bytes.
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* Debug IMA with alpha pointer
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* Support fused amax kernels with NVFP4 quantization
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* Disable fused amax with cuDNN LayerNorm kernel
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* Add NVFP4 cases to distributed tests for TE ops
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* Change assert to NVTE_CHECK in the hadamard cast fusion
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* Fix compile error
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* Use global thread IDs for Philox subsequences
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* Add shape checks for NVFP4 cast kernels
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* Do not fuse amax if cuDNN normalization is forced by envvar
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* add checks to cuda kernel launch and cuda API calls
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* Remove exceptions from destructors
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* fix weired dispatch in ln/rmsnorm
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Add launch bounds to swizzle kernel, use empty scale inv
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* for loop
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* bulk alloc
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* multi-tensor swizzle
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* pad zeros in swizzle kernels
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* unify single- and multi-tensor swizzle
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* fix empty tensor list
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* fix bug for col swizzle
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* check context & fix signifiers
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* Changed the Tensor allocation strategy
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* Fixes
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* Disable debug flag
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* Fix the double free error
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* Fix
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* Fixed pyTorch recipe extension
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* Fix
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* Fix
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* Hide TensorAllocator and fix the usage in LayerNorm
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* Cleaning
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* Fix
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* Fix permutation
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