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Signed-off-by: wenjh <wenjh@sugon.com>

Same intention of commit 3e38a2ea

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This commit is to improve acc.
Signed-off-by: wenjh <wenjh@sugon.com>

quantize_transpose_vector_blockwise function use lds exceeding 64kb when
input type is fp32. But max size of lds in dcu is 64kb, thus we use lds
as bfp16 for workaround.
Signed-off-by: wenjh <wenjh@sugon.com>

Signed-off-by: wenjh <wenjh@sugon.com>

Use ocp fp8.
Workaround: test_cast_float8blockwise.cu link wrong std::max
Signed-off-by: wenjh <wenjh@sugon.com>

Signed-off-by: wenjh <wenjh@sugon.com>

Signed-off-by: wenjh <wenjh@sugon.com>

Signed-off-by: wenjh <wenjh@sugon.com>

* Cleanup runtime library loading
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* Better comments and logic
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* Fix catching stray builds
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* Fix missing fw case
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* minor grammar
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* Fix duplicate SO for editable installs
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* Better comment for build ext
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* Improve error msg
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Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

Add rules of cuda_runtime.h, cuda_driver.h and cuda_nvml.h to hip.
Signed-off-by: wenjh <wenjh@sugon.com>

* First pass refactor
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

* first pass
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* core compiles
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* Fix
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* Fix test
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* Move grad outside autocast
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* Fix kv cache
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* Change src file name in cmake
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* Move comment
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* Move comments around
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* more movement
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* move
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Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

Default use of hipMallocAsync rather than hipMalloc in rocblas_gemm and
add support of fp16_fp16_fp32 in rocblas_gemm.
Signed-off-by: wenjh <wenjh@sugon.com>

* Initial work toward restoring UB support in te.Sequential
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* Minor tweaks
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* Initial impl of backward UB linear in te.Sequential
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* Debug UB linear backward with no quantization

dgrad GEMM + dx RS is still broken.
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* Fix chunk dims for dgrad GEMM + dx RS
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* Debugging MXFP8 UB cases

Still failing with dy AG + wgrad GEMM
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* Fix incorrect usage for GEMM input with block-scaled FP8
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* Fix RS out dims
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* Restore support for internal quantized tensors
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* Add tests for MXFP8 GEMM with UB
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* Debug test failures
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Fix launch params are larger than launch bounds(256) for kernels in
rocm_gemm.cu
Signed-off-by: wenjh <wenjh@sugon.com>

* Move multi tensors kernels from PyTorch extensions to core
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* Add int16 type to core (for storing fp32 param remainders)
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* Fix core build
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* same fix to scale
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* Fix perf, memory, vars
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* Re-add device guard for multi-device
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* Fix junk output dtype for non-per tensor
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* Fixes for test and upgrade mcore version
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* Fix core tests
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Debug UB conversion function from NVTEShape to std::vector
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[RocblasGemm] Provide support of AB(bf16)D(fp32)
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Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

* Reapply "Allow NVTEShape to own data." (#1703)

This reverts commit 91405eb4

.
Signed-off-by: Keith Wyss <kwyss@nvidia.com>

* Update code so that data is replaced by an array.
Signed-off-by: Keith Wyss <kwyss@nvidia.com>

* Specify unambiguous Tensor constructor in tests.
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* Fix assumption in test of 2D shape.
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* Remove row and col
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* Add support for nvidia cu* lib wheels
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* Fix
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* Loose
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Ref params of rmsnorm will make program corruption with 'nil' error.
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Fixes #1692
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Introduce nvte_memset to provide a fill kernel that is faster than cudaMemsetAsync for small sizes (#1716)

* nvte_memset fills single float value
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* Support larger sizes than a single value and add tests
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