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* check in per-tensor current scaling full recipe
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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setup basics of current scaling quantizer in python level
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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Signed-off-by: zhongboz <zhongboz@nvidia.com>

add test case for current scaling dequantize
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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Signed-off-by: zhongboz <zhongboz@nvidia.com>

finish linear layer fwd bwd test, determined error with bf16
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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achieved zero tolerance for Linear by specify gemm use_split_accumulator config
Signed-off-by: zhongboz <zhongboz@nvidia.com>

enable layernormlinear with current scaling, pass bitwise test
Signed-off-by: zhongboz <zhongboz@nvidia.com>

refactor test case code
Signed-off-by: zhongboz <zhongboz@nvidia.com>

make current scaling quantizers distrbuted, pass distributed linear&layernormlinear tests
Signed-off-by: zhongboz <zhongboz@nvidia.com>

bug fix: use cached fp8 recipe in backward
Signed-off-by: zhongboz <zhongboz@nvidia.com>

fix layernorm_mlp with current scaling, fix activation_helper with current scaling
Signed-off-by: zhongboz <zhongboz@nvidia.com>

support detailed numerical settings from recipe to quantization kernel
Signed-off-by: zhongboz <zhongboz@nvidia.com>

resolving MR comments
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recipe naming
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* resolve mr comments, remove IS_CURRENT_SCALING template from kernels
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* resolve mr comments, make current scaling c++ test cases
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* add current scaling to test_numerics.py, skip act recomp and grouped linear
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* add benchmark for quantizer
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* add benchmarks for linear layer
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* bug fix, typo
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* resolve more mr comments
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* avoid potential race condition by not using from_blob to construct amax tensor in C++
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* resolve more comments
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* Debug linter warnings and license check
Signed-off-by: Tim Moon <tmoon@nvidia.com>

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* Debug import error in FP8 tensor test
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Debug compilation error with CUDA 12.1 for Turing
Signed-off-by: Tim Moon <tmoon@nvidia.com>

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* resolve mr comments, fix activation cast fusion
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* resolve comments, add NVTEQuantizationParams for compute scale
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* remove is_current_scaling check totally from common folder
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* remove benchmarks, will contribute in another repo
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* adjust cs default recipe config
Signed-off-by: zhongboz <zhongboz@nvidia.com>

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* adjust comments in test
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* Remove current scaling mode from core lib
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Refactor current-scaling-specific logic in core C++ lib

Move amax and scale update functions out of casting functions, and put into dedicated current-scaling source file. Add general API for accessing quantization config object.
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* [pre-commit.ci] auto fixes from pre-commit.com hooks

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* Add missing header in C++ tests
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* Disable test config with FP8 transpose on Blackwell
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* Fix compilation error in C++ test
Signed-off-by: Tim Moon <tmoon@nvidia.com>

---------
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Signed-off-by: Tim Moon <tmoon@nvidia.com>
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* Added TMA alignment check to cast_fp8_1D
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* Use tensor const-ref instead of tensor const-ptr
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* Use 64-bit offsets for cuDNN 9.5+
* Align workspace tensors to 16B.
* Fix bug where std::accumulate overflowed on large tensor shapes.
* Only support 64-bit offsets on arbitrary sequence length fp16 backend.
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* Perform scale-inv update in cast-transpose kernels
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Perform scale-inv update in cast and activation kernels
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* Perform sclae-inv update in LayerNorm and RMSNorm kernels
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* Perform scale-inv update after FP8 GEMMs
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* Fuse casts and scale-inv updates in linear module
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* Fuse casts and scale-inv updates in layernorm-linear module
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* Simplify kernel to update FP8 scale-inv
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* Fix typos
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* Debug amax update in layernorm kernels
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* [pre-commit.ci] auto fixes from pre-commit.com hooks

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* Debug test failures
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Debug ONNX export

Use quantization scaling factor in ONNX quantize op.
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Review suggestion from @ptrendx
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* Debug mismatched dtypes
Signed-off-by: Tim Moon <tmoon@nvidia.com>

---------
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* Apply formatting
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

* Apply formatting
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>

---------
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Use unsigned char for byte dtype
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* Do not include logging macros in installed C headers
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* Debug logging macros
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* Debug C++ tests

Use Google style for header includes.
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* Update CUDA driver macros

Incorporating changes from #389.
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* Use core error checking macros in PyTorch extensions

Hack to get around macro redefinition warning.
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* Fix missing arg when getting CUDA driver error string
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* Reuse logging header in frameworks
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---------
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* Initial implementation of NVRTC infrastructure
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Initial NVRTC impl for transpose

NVRTC gives compilation errors at runtime. Everything else compiles and passes tests as expected.
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Debug NVRTC transpose impl

NVRTC kernel compiles, runs, and passes tests with FP32.
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Use variadic template for kernel arguments in RTC kernel launch func
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* Refactoring

Added utility header for CUDA Runtime API. Optimized concat_strings function.
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* Add helper function for regex substitutions in strings
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* Add option to disable NVRTC support
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* Add support for header includes in NVRTC kernels
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* Access lazily-initialized CUDA driver lib and add option to specify CUDA header dir
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* Configure NVRTC transpose kernel with simple perf model
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* Revert change to tests
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* Style fixes
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* Add prime-valued test cases
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* Fix multiple definition error
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* Optimize NVRTC transpose kernel for small data sizes
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* Mention NVRTC in docs
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* Add unit tests for NVRTC and string utils
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* Add comment in install docs about NVRTC

Review suggestion from @nouiz
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* Debug perf model for RTC transpose kernel
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* Remove NVRTC discussion from docs
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* Require CUDA headers unless NVRTC is explicitly disabled
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* Use diagonal coords in transpose kernel to avoid partition camping
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* Use std::call_once for thread-safety
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* Minor fixes
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* Debug CMake error
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* Remove unnecessary call_once
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* Remove diagonal coordinates from transpose kernel
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* Use size_t indices instead of int
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* Review suggestions from @ptrendx

Check build-time CUDA include path for run-time CUDA headers. Handle case where CUDA context is initially uninitialized.
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---------
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* Add NVTX to TE modules
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* Fix
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* Fix pylint
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* Fix NVTX in _prepare_backward
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* Add NVTX to C API
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* Fix cpplint and link nvToolsExt
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* Add NVTX to GeGlu
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* Move the amax/scale/scale_inv into the TE Tensor struct.
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* Handle multi_cast_transpose
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* Changed softmax to new Tensor
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* First pass at the cpp tests
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* Round of fixes
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* Fix multi_cast_transpose
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* Fix cast_to_fp8
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* Make fused softmax kernels PyTorch independent
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* Address review comments
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* move get_batch_per_block to python
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* fix license in softmax.h
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