Commits · 063ef88d1af050b9076daaa5b92ed2d0018796fa · OpenDAS / TransformerEngine

29 Sep, 2025 1 commit

[Core][PyTorch] NVFP4 recipe (#2177) · 3f5b4754

Kirthi Shankar Sivamani authored Sep 29, 2025



* Add NVFP4 recipe
Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>
Co-authored-by: Frank Sun <frsun@nvidia.com>
Co-authored-by: Oleg Goncharov <ogoncharov@nvidia.com>
Co-authored-by: Zhongbo Zhu <zhongboz@nvidia.com>
Co-authored-by: Evgeny Tsykunov <etsykunov@nvidia.com>
Co-authored-by: Tim Moon <tmoon@nvidia.com>
Co-authored-by: Teddy Do <tdophung@nvidia.com>

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* Add MathDx dependency to GitHub builds
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* Suggestions from GitHub Copilot
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* Move 2x shape logic from core to PyTorch
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* Fix compilation errors with CUDA 12.1
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* SM 70 is not supported in CUDA 13
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* Typo
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* Revert "Move 2x shape logic from core to PyTorch"

This reverts commit f8b2a2d0111d9af690b43bb98ae448d9a430a185.
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Added dequantize kernel for FP4
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* Fix linter warning
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* Add NVFP4 support with fusible ops

Use logical tensor dims for PyTorch NVFP4 tensors. Temporarily add unfused dequantize impl. Fix bug where NVFP4 recipe was not configurable.
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* Fix logic for 2x shapes and move to PyTorch
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* Fix CG test model config
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* Debug NVFP4 tensor size function
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* Proper handling of the RNG state
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* Test SR properly
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* Fix workspace size for GEMM heuristic.
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* Fix compile error in C++ NVFP4 test

Some some numeric errors when blocks are all zero.
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* fix distrbuted test problem shape
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* proper assert dim for low precision AG TP
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* clean up duplicated code in nvfp4_utils.cuh
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* lint
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* pylint: disable=unused-argument
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* `nvte_cublas_gemm_v2` to take alpha pointer (#12)

* make nvte_cublas_gemm_v2 to take alpha/beta pointers
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* users are expected to pass a valid C_tensor
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* typos
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* API to have const float* alpha
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* Minor tweaks

Support arbitrary beta scales. Increase workspace to be aligned to 128 bytes.
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* Debug IMA with alpha pointer
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* Support fused amax kernels with NVFP4 quantization
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* Disable fused amax with cuDNN LayerNorm kernel
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* Add NVFP4 cases to distributed tests for TE ops
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* Change assert to NVTE_CHECK in the hadamard cast fusion
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* Fix compile error
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* Use global thread IDs for Philox subsequences
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* Add shape checks for NVFP4 cast kernels
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* Do not fuse amax if cuDNN normalization is forced by envvar
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3f5b4754

04 Sep, 2025 1 commit

[PyTorch][CUDA Graph] Fix FP8 Weight Quantization Cache under CUDA Graph (#2119) · 0f68f7b2

Zhongbo Zhu authored Sep 04, 2025



* add noop to comp amax
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* fix for fp8 blockwise recipe
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* resolve comments
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---------
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0f68f7b2

06 Jun, 2025 1 commit

[PyTorch] FP8 Subchannel Recipe With FP8 Gather And Configurable Scaling... · 9985b02c

Zhongbo Zhu authored Jun 05, 2025


[PyTorch] FP8 Subchannel Recipe With FP8 Gather And Configurable Scaling Factor Tensor Swizzling (#1707)

* functional kernel for columnwise + no-transpose option, still hacky
Signed-off-by: zhongboz <zhongboz@nvidia.com>

* pass all quantizer unit tests
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* refactor, add gemm ready api
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* make format options private members, simplify api
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* swizzle scales right before gemm
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* bug fix of single layer test
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* attempt to fix lint issue
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* fp8 gather pass, need minor refine
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* fix return_layernorm_output_gathered case
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* Implement dequantize for compact 1D blocks.
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* lint again
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* resolve rebase issues
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* fix lint
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9985b02c

10 Apr, 2025 1 commit

Blockwise scaling linear quantization recipe (#1559) · a8f0fe03

kwyss-nvidia authored Apr 10, 2025



* Add GEMM logic for blockwise quantized tensors.

GEMM test cases included in pytorch integration.
Signed-off-by: Keith Wyss <kwyss@nvidia.com>

* Update NVTE_BLOCK_SCALING for GEMM.
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* Gate feature on CUDA 12.9
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* Gemm typo.
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* Remove unecessary type converter change.
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* Reflect epilogue availability and test supported epilogues.
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* GEMM simplifications from recipe branch.
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* Format py code.
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* Update GEMM DGelu tests to match support depending on output dtype.
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* Force pow2Scales in GEMM
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* Add GEMM test to pytorch test suite.
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* Add copyright to GEMM test.
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* Update import for GEMM test.
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* Add license.
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* Update test gemm supported predicate.
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* Use sgemm like interfaces and naming.
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* Rewrite GEMM comment.
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* MR Feedback.
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* Recipe setup for Linear modules.
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* Use 12.9 feature test.
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* Run against tensor dumps from internal library.
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* Update FIXME to TODO with linked issue.
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* Update full recompute feature to save recipe.

The recompute context uses the same recipe
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* MR Feedback. Avoid reusing quantizer objects.
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* Update for PP bug.
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* Update force_power_of_2 scales in the recipe.
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* Update usage method to satisfy upstream changes.
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* fix subchannel recipe in distributed test with bf16 gather
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* Update test import.
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* support columnwise only mode to 1D quantize kernel
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* Format and move enum
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* Skip alloc.
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* Document and type code.
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* Dont set high precision dtype.
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* Add test for sanity and CG; fix CG for sequential?
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* Keep make_quantizers API stable

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* Fix import name.
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* Rename recipe method.
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* Skip grouped linear sanity test.
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* Set usage before BF16 gather.
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* Simplify layernorm linear
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* Cleanup layernorm linear.
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* LayerNorm linear bwd gather logic.
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* Communication updates.
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a8f0fe03

04 Apr, 2025 1 commit

Blockwise float8 quantizer and quantized tensor class (#1513) · 1bbeab1c

kwyss-nvidia authored Apr 03, 2025



* Blockwise float8 quantizer and quantized tensor class.

The classes are configurable for 128x128 blocksize
and 1x128 blocksize via setting block_scaling_dim == 2,1 respectively.

Scale tensors are stored in a format emenable for matrix multiplication,
however the integration of matmul is deferred as a separate story.

Fusions of quantization and DBIAS or activation functions are not yet
implemented, and the dequantization is currently implemented in torch.

Tests for quantization are included in C++ and pytorch layers, with
exact comparison to reference quantizer behavior as well as an attempt
to hit interesting branches through the API such as tensor creation
in pytorch and CPP and dequantization of row and columnwise usage.

Two CUDA kernels for quantization are included, and are direct ports
of equivalents in the kitchen repository, where a subchannel recipe
has been used for end to end training.
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* Apply linting changes.
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* Alignment for 1D scaling for GEMM edge case.
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* MR feedback.
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* Change API name.
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* Fix merge conflict with name change.
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* Use common tensor map API.
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* Change API to use two scaling mode enums.
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* Fix typo.
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* Update some call sites.
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* Tests for torch tensor API surface.

Since the quantized tensor is a tensor
subclass, these tests exercise torch hooks.
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* Reuse scale calculation between quantizer refs.
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* Save memory by dropping reference to saved tensors.

Issues previously observed are solved.
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* Remove constexpr parameters from kernel.

Code size is reduced with fewer constexpr params.
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* Merge conflict from rebase.
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* Add shape implementations for block scaling.

nvte_shape was added upstream. Logic added
for block scaled fp8.
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* Move benchmark to te_playground
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* Remove amax_epsilon and pow_2_scales from tensor.

Hardcodes the default values.
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* Lint changes.
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* Fixup MR changes that broke.
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* Safer ifdef in kernel.
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* Documentation prose.
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* Reuse compute_scale function from Current Scaling.
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* Bugfix on inf_value scale refactor.
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* Update pytest list.
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* Add copyright to reference scale calc.
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* Use TypeInfo
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* Update CS scale update test to use updated ref impl
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Update JAX scaling mode enum
Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Skip tests on Lovelace
Signed-off-by: Tim Moon <tmoon@nvidia.com>

---------
Signed-off-by: Keith Wyss <kwyss@nvidia.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>
Co-authored-by: Tim Moon <tmoon@nvidia.com>
Co-authored-by: Tim Moon <4406448+timmoon10@users.noreply.github.com>

1bbeab1c

07 Feb, 2025 1 commit
- Update main branch with TE 2.0 code, update version to 2.1.0.dev0 · 544dd14b
  Przemek Tredak authored Feb 07, 2025
```
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
```
  544dd14b