GitLab

* Fix the tail loading issue.

* Modify the sync offset.

* Fix warp synchronization.

* Another fix.

* Add automatic warp count control for low-latency dispatch

* Add automatic warp count control for low-latency combine

* More assertions

let the sender SM use the channel_id, and the receiver SM use channel_id + num_channels

* Use `pynvml` to detect NVLink connections

* Add a TODO

* Add shutdown

* Fix comments

* Update README

* Update `setup.py`

* Fix headers

* Add `DISABLE_NVSHMEM` for APIs

* Fix launch

* Fix TMA settings

* Fix TMA usages

* Fix dlink

* Separate layout kernels

* Update version

* Add `is_sm90_compiled`

* Fix tests

* Add NVLink connection checks

* Update README

* Fix tests

* Add some comments

* Minor fix

* Minor fix

* Fix bugs

* Fully remove FIFO slots

* Fully remove FIFO buffers

* Minor fix styles

* Fix some typos

* Bugs fixed

* Cleanup `ibgda_poll_cq`

remove the dependency of gdrcopy

Signed-off-by: youkaichao <youkaichao@gmail.com>

Signed-off-by: youkaichao <youkaichao@gmail.com>

* Add low-latency kernel usage flag

* Update comments

Allow using MNNVL

* Update CMake files

* Use TMA instead of LD/ST for intranode dispatch

* Use TMA instead of LD/ST for intranode combine

* Adjust configs

* Test default configs as well

* More warps for combine

* Add inter-thread fence

* Enable more warps

* Do not use TMA for senders

* Update configs

* Remove useless wait

Co-authored-by: Shangyan Zhou <sy.zhou@deepseek.com>

Fix notify_dispatch: using warp 0 to issue send

Signed-off-by: wzc.wuzhicheng <wzc.wuzhicheng@linux.alibaba.com>

Low-latency P2P code cleanup and bug fixed

* Add 10.0 to TORCH_CUDA_ARCH_LIST
Signed-off-by: Guyue Huang <guyueh@nvidia.com>

* Revert csrc/CMakeLists change; in setup.py make TORCH_CUDA_ARCH_LIST configurable
Signed-off-by: Guyue Huang <guyueh@nvidia.com>

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Signed-off-by: Guyue Huang <guyueh@nvidia.com>

Support hidden size 4096

Co-authored-by: zhyncs <me@zhyncs.com>
Co-authored-by: yinfan98 <1106310035@qq.com>

Feat: enhance nvidia peer memory detection

Shuffling the starting index of target rank for different ranks and channels