---
id: pr-tensorrt-llm-10987
repo: NVIDIA/TensorRT-LLM
pr: 10987
title: '[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth'
author: sherry-1001
date: '2026-01-27'
url: https://github.com/NVIDIA/TensorRT-LLM/pull/10987
source_category: upstream-code
architectures:
- sm100
tags:
- arch_pipeline
- benchmark_test
- compiler_runtime
- cute dsl
- gemm_quant
- moe_routing
techniques:
- async-copy
- fine-grained-quantization
- kernel-fusion
- pipeline-stages
hardware_features:
- blackwell
- tma
kernel_types:
- compiler
- gemm
- moe
- reduction
- runtime
languages:
- cuda-cpp
- cute-dsl
captured_at: '2026-05-16'
status: merged
merge_sha: fae4985797b1b4bdb7683d281c19b6ff56f414f9
inclusion_reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.
changed_paths:
- tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py
- tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
- tensorrt_llm/_torch/cute_dsl_kernels/blackwell/utils.py
artifact_dir: evidence/pull-bundles/tensorrt-llm/gh-10987
head_ref_oid: 731d0205dc8d75baaf947312c7df1bbd1ebb363f
---
# [TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth

- Repository: `NVIDIA/TensorRT-LLM`
- PR: [10987](https://github.com/NVIDIA/TensorRT-LLM/pull/10987)
- Decision: `Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.`
- Reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.

## Changed Paths

- `tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`
- `tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py`
- `tensorrt_llm/_torch/cute_dsl_kernels/blackwell/utils.py`

## Evidence Bundle

`evidence/pull-bundles/tensorrt-llm/gh-10987`
