---
id: pr-tensorrt-llm-10339
repo: NVIDIA/TensorRT-LLM
pr: 10339
title: '[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.'
author: hyukn
date: '2026-01-08'
url: https://github.com/NVIDIA/TensorRT-LLM/pull/10339
source_category: upstream-code
architectures:
- sm100
tags:
- compiler_runtime
- cute dsl
- gemm_quant
- memory_primitives
- scheduler_autotune
techniques:
- autotuning
- fine-grained-quantization
- tile-scheduling
hardware_features:
- fp4
- nvfp4
kernel_types:
- compiler
- gemm
- memory
- scheduler
languages:
- cuda-cpp
- cute-dsl
captured_at: '2026-05-16'
status: merged
merge_sha: 09d9878385a7ac52c11491e6981d9f98a326449d
inclusion_reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.
changed_paths:
- tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py
artifact_dir: evidence/pull-bundles/tensorrt-llm/gh-10339
head_ref_oid: 1d1c8a8eee2fcd32b4028933f750b53f5762aba7
---
# [TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.

- Repository: `NVIDIA/TensorRT-LLM`
- PR: [10339](https://github.com/NVIDIA/TensorRT-LLM/pull/10339)
- Decision: `Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.`
- Reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.

## Changed Paths

- `tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`

## Evidence Bundle

`evidence/pull-bundles/tensorrt-llm/gh-10339`
