---
id: pr-tensorrt-llm-8620
repo: NVIDIA/TensorRT-LLM
pr: 8620
title: '[None][feat] Enable nvfp4 cuda core for sm120'
author: Njuapp
date: '2025-10-29'
url: https://github.com/NVIDIA/TensorRT-LLM/pull/8620
source_category: upstream-code
architectures:
- sm100
tags:
- gemm_quant
- userbuffers
techniques:
- fine-grained-quantization
hardware_features:
- fp4
- nvfp4
kernel_types:
- gemm
languages:
- cuda-cpp
captured_at: '2026-05-16'
status: merged
merge_sha: 15c293a90b9c461a78f5ed0ad5ff559947372727
inclusion_reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.
changed_paths:
- cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/cudaCoreGemmNVFP4.cu
- cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/cudaCoreGemmNVFP4.h
- cpp/tensorrt_llm/thop/CMakeLists.txt
- cpp/tensorrt_llm/thop/cudaNvfp4MM.cpp
- tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py
- tensorrt_llm/_torch/modules/linear.py
- tests/unittest/_torch/thop/parallel/test_fp4_linear.py
artifact_dir: evidence/pull-bundles/tensorrt-llm/gh-8620
head_ref_oid: c8a1abde7eaa121cd53b0f55d57b251a4f8903a4
---
# [None][feat] Enable nvfp4 cuda core for sm120

- Repository: `NVIDIA/TensorRT-LLM`
- PR: [8620](https://github.com/NVIDIA/TensorRT-LLM/pull/8620)
- Decision: `Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.`
- Reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.

## Changed Paths

- `cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/cudaCoreGemmNVFP4.cu`
- `cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/cudaCoreGemmNVFP4.h`
- `cpp/tensorrt_llm/thop/CMakeLists.txt`
- `cpp/tensorrt_llm/thop/cudaNvfp4MM.cpp`
- `tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py`
- `tensorrt_llm/_torch/modules/linear.py`
- `tests/unittest/_torch/thop/parallel/test_fp4_linear.py`

## Evidence Bundle

`evidence/pull-bundles/tensorrt-llm/gh-8620`
