---
id: pr-tilelang-1899
repo: tile-ai/tilelang
pr: 1899
title: '[BugFix] add target context and avoid redundant re-lowering in TLCPUSourceWrapper'
author: xyyy1420
date: '2026-03-05'
url: https://github.com/tile-ai/tilelang/pull/1899
source_category: upstream-code
architectures:
- sm100
tags:
- matmul
techniques: []
hardware_features: []
kernel_types:
- gemm
languages: []
captured_at: '2026-05-16'
status: merged
merge_sha: 00267e43aafcff3047f93e4e8373f68c081728e9
inclusion_reason: Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.
changed_paths:
- testing/python/cpu/test_tilelang_cpu_gemm.py
- tilelang/jit/adapter/wrapper.py
artifact_dir: evidence/pull-bundles/tilelang/gh-1899
head_ref_oid: ecd1a14e53b2281d134dc617a53abe87418538a0
---
# [BugFix] add target context and avoid redundant re-lowering in TLCPUSourceWrapper

- Repository: `tile-ai/tilelang`
- PR: [1899](https://github.com/tile-ai/tilelang/pull/1899)
- Decision: `Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.`
- Reason: Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.

## Changed Paths

- `testing/python/cpu/test_tilelang_cpu_gemm.py`
- `tilelang/jit/adapter/wrapper.py`

## Evidence Bundle

`evidence/pull-bundles/tilelang/gh-1899`
