---
id: pr-tensorrt-llm-13740
repo: NVIDIA/TensorRT-LLM
pr: 13740
title: '[https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5'
author: yijingl-nvidia
date: '2026-05-14'
url: https://github.com/NVIDIA/TensorRT-LLM/pull/13740
source_category: upstream-code
architectures:
- sm100
tags:
- benchmark_test
- blackwell
- cutlass
- gemm_quant
- moe_routing
- routing
techniques:
- fine-grained-quantization
hardware_features:
- blackwell
kernel_types:
- gemm
- moe
languages:
- cuda-cpp
- cute-dsl
captured_at: '2026-05-16'
status: merged
merge_sha: 7d2bed7820cee5a363807b55fe22f660e1f43b0b
inclusion_reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.
changed_paths:
- cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3RouterGemm.cu
- cpp/tensorrt_llm/thop/dsv3RouterGemmOp.cpp
- tests/unittest/_torch/thop/parallel/test_dsv3_router_gemm.py
artifact_dir: evidence/pull-bundles/tensorrt-llm/gh-13740
head_ref_oid: 4990d7704a37a32f6428a3be101a805af44e0e92
---
# [https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5

- Repository: `NVIDIA/TensorRT-LLM`
- PR: [13740](https://github.com/NVIDIA/TensorRT-LLM/pull/13740)
- Decision: `Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.`
- Reason: Inspect scale layout, accumulator type, tile/schedule choice, epilogue fusion, and partial-tile guards before deriving a candidate.

## Changed Paths

- `cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3RouterGemm.cu`
- `cpp/tensorrt_llm/thop/dsv3RouterGemmOp.cpp`
- `tests/unittest/_torch/thop/parallel/test_dsv3_router_gemm.py`

## Evidence Bundle

`evidence/pull-bundles/tensorrt-llm/gh-13740`
