---
id: pr-tilelang-2187
repo: tile-ai/tilelang
pr: 2187
title: '[WIP] Handle CuTeDSL FP4 torch dtype'
author: zihaomu
date: '2026-05-12'
url: https://github.com/tile-ai/tilelang/pull/2187
source_category: upstream-code
architectures:
- sm100
tags:
- cutlass
- fp4
techniques: []
hardware_features:
- fp4
kernel_types: []
languages:
- cute-dsl
captured_at: '2026-05-16'
status: merged
merge_sha: e8386483626652f96dde3f69c56dd7dc2cf589b2
inclusion_reason: Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.
changed_paths:
- examples/conftest.py
- tilelang/jit/adapter/cutedsl/wrapper.py
artifact_dir: evidence/pull-bundles/tilelang/gh-2187
head_ref_oid: b92e7c0e74ab5c843687ede936958a7d13a94005
---
# [WIP] Handle CuTeDSL FP4 torch dtype

- Repository: `tile-ai/tilelang`
- PR: [2187](https://github.com/tile-ai/tilelang/pull/2187)
- Decision: `Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.`
- Reason: Search-matched CUDA kernel optimization PR; materialize diff/source before synthesis.

## Changed Paths

- `examples/conftest.py`
- `tilelang/jit/adapter/cutedsl/wrapper.py`

## Evidence Bundle

`evidence/pull-bundles/tilelang/gh-2187`
