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gaoqiong
composable_kernel
Commits
c7c47fd7
Commit
c7c47fd7
authored
Aug 10, 2023
by
Bartlomiej Wroblewski
Browse files
Merge branch 'develop' into bwroblew/dpp8
parents
f8eb91d7
578142db
Changes
183
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20 changed files
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212 additions
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562 deletions
+212
-562
library/src/tensor_operation_instance/gpu/conv2d_fwd/device_conv2d_fwd_xdl_nhwc_kyxc_nhwk_int8_instance.cpp
...wd/device_conv2d_fwd_xdl_nhwc_kyxc_nhwk_int8_instance.cpp
+2
-1
library/src/tensor_operation_instance/gpu/elementwise_normalization/CMakeLists.txt
...ion_instance/gpu/elementwise_normalization/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm/CMakeLists.txt
...ary/src/tensor_operation_instance/gpu/gemm/CMakeLists.txt
+34
-31
library/src/tensor_operation_instance/gpu/gemm/device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp
...f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp
+1
-1
library/src/tensor_operation_instance/gpu/gemm_add_add_fastgelu/CMakeLists.txt
...eration_instance/gpu/gemm_add_add_fastgelu/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm_add_fastgelu/CMakeLists.txt
...r_operation_instance/gpu/gemm_add_fastgelu/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm_add_relu_add_layernorm/CMakeLists.txt
...n_instance/gpu/gemm_add_relu_add_layernorm/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm_bilinear/CMakeLists.txt
...ensor_operation_instance/gpu/gemm_bilinear/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm_fastgelu/CMakeLists.txt
...ensor_operation_instance/gpu/gemm_fastgelu/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/gemm_streamk/CMakeLists.txt
...tensor_operation_instance/gpu/gemm_streamk/CMakeLists.txt
+2
-0
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instance.cpp
...e_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instance.cpp
+21
-98
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instance.cpp
...ce_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instance.cpp
+21
-98
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instance.cpp
...ce_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instance.cpp
+21
-97
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instance.cpp
...e_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instance.cpp
+21
-94
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_common.hpp
...u/grouped_conv2d_fwd/device_grouped_conv2d_fwd_common.hpp
+0
-53
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
..._grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
+1
-1
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
..._grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
+1
-1
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_bf16_instance.cpp
...rouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_bf16_instance.cpp
+25
-29
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
...grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
+25
-29
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
...grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
+25
-29
No files found.
library/src/tensor_operation_instance/gpu/conv2d_fwd/device_conv2d_fwd_xdl_nhwc_kyxc_nhwk_int8_instance.cpp
View file @
c7c47fd7
...
...
@@ -8,7 +8,7 @@
#include "ck/tensor_operation/gpu/device/impl/device_conv2d_fwd_xdl_nhwc_kyxc_nhwk.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#ifdef __int8__
namespace
ck
{
namespace
tensor_operation
{
namespace
device
{
...
...
@@ -123,3 +123,4 @@ void add_device_conv2d_fwd_xdl_nhwc_kyxc_nhwk_int8_instances(
}
// namespace device
}
// namespace tensor_operation
}
// namespace ck
#endif
library/src/tensor_operation_instance/gpu/elementwise_normalization/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_elementwise_normalization_instance
device_elementwise_normalization_f16_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm/CMakeLists.txt
View file @
c7c47fd7
...
...
@@ -99,36 +99,39 @@ endif()
add_instance_library
(
device_gemm_instance
${
GEMM_INSTANCES
}
)
set
(
ENABLE_PIPELINE_V2_OPT OFF
)
if
(
ENABLE_PIPELINE_V2_OPT
)
set
(
MAX_ILP_OPTS
-mllvm
-amdgpu-enable-max-ilp-scheduling-strategy
)
set
(
WAVES_PER_EU_DEFS
CK_USE_WAVES_PER_EU=1
CK_MIN_WAVES_PER_EU=1
CK_MAX_WAVES_PER_EU=1
)
set
(
IGLP_OPT_DEFS
CK_EXPERIMENTAL_PIPELINE_V2_IGLP_OPT=1
)
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
set
(
ENABLE_PIPELINE_V2_OPT OFF
)
if
(
ENABLE_PIPELINE_V2_OPT
)
set
(
MAX_ILP_OPTS
-mllvm
-amdgpu-enable-max-ilp-scheduling-strategy
)
set
(
WAVES_PER_EU_DEFS
CK_USE_WAVES_PER_EU=1
CK_MIN_WAVES_PER_EU=1
CK_MAX_WAVES_PER_EU=1
)
set
(
IGLP_OPT_DEFS
CK_EXPERIMENTAL_PIPELINE_V2_IGLP_OPT=1
)
# layout=NT
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
";;"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
# layout=NN
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
"
${
MAX_ILP_OPTS
}
"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
# layout=TT
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
"
${
MAX_ILP_OPTS
}
"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
"
)
# layout=TN
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
"
${
MAX_ILP_OPTS
}
"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
endif
(
ENABLE_PIPELINE_V2_OPT
)
# layout=NT
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
";;"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
# layout=NN
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
"
${
MAX_ILP_OPTS
}
"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
# layout=TT
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
";;"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
# layout=TN
set_source_files_properties
(
device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
COMPILE_OPTIONS
"
${
MAX_ILP_OPTS
}
"
COMPILE_DEFINITIONS
"
${
WAVES_PER_EU_DEFS
}
;
${
IGLP_OPT_DEFS
}
"
)
endif
(
ENABLE_PIPELINE_V2_OPT
)
endif
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
library/src/tensor_operation_instance/gpu/gemm/device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp
View file @
c7c47fd7
...
...
@@ -18,7 +18,7 @@ using Instances =
//##########| Type| Type| Type| Type| | | | Elementwise| Elementwise| Elementwise|Specialization| Size| Block| Block| Block| | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| SrcDstVectorDim| DstScalar| | | |
//##########| | | | | | | | Operation| Operation| Operation| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | | PerVector| | | |
//##########| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGemmXdl
<
F16
,
F16
,
F16
,
F32
,
Row
,
Row
,
Row
,
PassThrough
,
PassThrough
,
PassThrough
,
GemmDefault
,
256
,
64
,
128
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
true
,
S
<
4
,
64
,
1
>
,
S
<
0
,
2
,
1
>
,
S
<
0
,
2
,
1
>
,
1
,
2
,
8
,
true
,
7
,
1
,
1
,
LoopScheduler
::
Default
,
PipelineVersion
::
v2
>
DeviceGemmXdl
<
F16
,
F16
,
F16
,
F32
,
Row
,
Row
,
Row
,
PassThrough
,
PassThrough
,
PassThrough
,
GemmDefault
,
256
,
64
,
128
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
8
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
true
,
S
<
4
,
64
,
1
>
,
S
<
0
,
2
,
1
>
,
S
<
0
,
2
,
1
>
,
1
,
2
,
8
,
true
,
7
,
1
,
1
,
LoopScheduler
::
Default
,
PipelineVersion
::
v2
>
#endif
// clang-format on
>
;
...
...
library/src/tensor_operation_instance/gpu/gemm_add_add_fastgelu/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_add_add_fastgelu_instance
device_gemm_add_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_f16_km_kn_mn_mn_mn_instance.cpp
device_gemm_add_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_f16_km_nk_mn_mn_mn_instance.cpp
device_gemm_add_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_f16_mk_kn_mn_mn_mn_instance.cpp
device_gemm_add_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_f16_mk_nk_mn_mn_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm_add_fastgelu/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_add_fastgelu_instance
device_gemm_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_km_kn_mn_mn_instance.cpp
device_gemm_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_km_nk_mn_mn_instance.cpp
device_gemm_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_mk_kn_mn_mn_instance.cpp
device_gemm_add_fastgelu_xdl_c_shuffle_f16_f16_f16_f16_mk_nk_mn_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm_add_relu_add_layernorm/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_add_relu_add_layernorm_instance
device_gemm_add_relu_add_xdl_c_shuffle_layernorm_f16_km_kn_mn_mn_mn_instance.cpp
device_gemm_add_relu_add_xdl_c_shuffle_layernorm_f16_km_nk_mn_mn_mn_instance.cpp
device_gemm_add_relu_add_xdl_c_shuffle_layernorm_f16_mk_kn_mn_mn_mn_instance.cpp
device_gemm_add_relu_add_xdl_c_shuffle_layernorm_f16_mk_nk_mn_mn_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm_bilinear/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_bilinear_instance
device_gemm_bilinear_xdl_c_shuffle_f16_f16_f16_f16_km_kn_mn_mn_instance.cpp
device_gemm_bilinear_xdl_c_shuffle_f16_f16_f16_f16_km_nk_mn_mn_instance.cpp
device_gemm_bilinear_xdl_c_shuffle_f16_f16_f16_f16_mk_kn_mn_mn_instance.cpp
device_gemm_bilinear_xdl_c_shuffle_f16_f16_f16_f16_mk_nk_mn_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm_fastgelu/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_fastgelu_instance
device_gemm_fastgelu_xdl_c_shuffle_f16_f16_f16_km_kn_mn_instance.cpp
device_gemm_fastgelu_xdl_c_shuffle_f16_f16_f16_km_nk_mn_instance.cpp
device_gemm_fastgelu_xdl_c_shuffle_f16_f16_f16_mk_kn_mn_instance.cpp
device_gemm_fastgelu_xdl_c_shuffle_f16_f16_f16_mk_nk_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/gemm_streamk/CMakeLists.txt
View file @
c7c47fd7
if
(
DTYPES MATCHES
"fp16"
OR NOT DEFINED DTYPES
)
add_instance_library
(
device_gemm_streamk_instance
# device_gemm_xdl_streamk_f32_f32_f32_mk_kn_mn_instance.cpp
# device_gemm_xdl_streamk_f32_f32_f32_mk_nk_mn_instance.cpp
...
...
@@ -8,3 +9,4 @@ add_instance_library(device_gemm_streamk_instance
# device_gemm_xdl_streamk_f16_f16_f16_km_kn_mn_instance.cpp
# device_gemm_xdl_streamk_f16_f16_f16_km_nk_mn_instance.cpp
)
endif
()
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instance.cpp
View file @
c7c47fd7
// SPDX-License-Identifier: MIT
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include <cstdlib>
#include "ck/ck.hpp"
#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_fwd_multiple_d_xdl_cshuffle.hpp"
#include "ck/tensor_operation/gpu/device/convolution_forward_specialization.hpp"
#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/device_grouped_conv_fwd_xdl_instance.hpp"
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
namespace
ck
{
...
...
@@ -17,94 +9,6 @@ namespace tensor_operation {
namespace
device
{
namespace
instance
{
using
BF16
=
ck
::
bhalf_t
;
using
F32
=
float
;
using
Empty_Tuple
=
ck
::
Tuple
<>
;
template
<
ck
::
index_t
...
Is
>
using
S
=
ck
::
Sequence
<
Is
...
>
;
using
GNWC
=
ck
::
tensor_layout
::
convolution
::
GNWC
;
using
GKXC
=
ck
::
tensor_layout
::
convolution
::
GKXC
;
using
GNWK
=
ck
::
tensor_layout
::
convolution
::
GNWK
;
using
PassThrough
=
ck
::
tensor_operation
::
element_wise
::
PassThrough
;
static
constexpr
auto
ConvFwdDefault
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Default
;
static
constexpr
auto
ConvFwd1x1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Pad0
;
static
constexpr
auto
ConvFwd1x1S1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Stride1Pad0
;
static
constexpr
auto
GemmMNKPadding
=
ck
::
tensor_operation
::
device
::
GemmSpecialization
::
MNKPadding
;
// Compilation parameters for in[g, n, wi, c] * wei[g, k, x, c] = out[g, n, wo, k]
using
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instances
=
std
::
tuple
<
// clang-format off
// Default
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
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GNWK
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BF16
,
BF16
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Empty_Tuple
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BF16
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PassThrough
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PassThrough
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PassThrough
,
ConvFwdDefault
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GemmMNKPadding
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1
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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GKXC
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Empty_Tuple
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BF16
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Empty_Tuple
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PassThrough
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GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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GNWC
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Empty_Tuple
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BF16
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BF16
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Empty_Tuple
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PassThrough
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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// Filter1x1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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GKXC
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Empty_Tuple
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GNWK
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
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128
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
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BF16
,
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,
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,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
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32
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
,
GNWK
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BF16
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BF16
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,
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,
Empty_Tuple
,
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PassThrough
,
PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
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,
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PassThrough
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,
GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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GKXC
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Empty_Tuple
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GNWK
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BF16
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PassThrough
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PassThrough
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
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// Filter1x1Stride1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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Empty_Tuple
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ConvFwd1x1S1P0
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GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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PassThrough
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,
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,
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,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
64
,
32
,
8
,
8
,
32
,
32
,
2
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
64
,
32
,
8
,
8
,
32
,
32
,
2
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
32
,
32
,
8
,
8
,
32
,
32
,
2
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
32
,
128
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
32
,
32
,
8
,
8
,
32
,
32
,
2
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
BF16
,
BF16
,
F32
,
BF16
,
Empty_Tuple
,
BF16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
32
,
64
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
// clang-format on
>
;
void
add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instances
(
std
::
vector
<
std
::
unique_ptr
<
DeviceGroupedConvFwdMultipleD
<
1
,
GNWC
,
...
...
@@ -120,7 +24,26 @@ void add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_bf16_instances
{});
device_grouped_conv_fwd_xdl_bf16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_bf16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_bf16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1S1P0
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instance.cpp
View file @
c7c47fd7
// SPDX-License-Identifier: MIT
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include <cstdlib>
#include "ck/ck.hpp"
#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_fwd_multiple_d_xdl_cshuffle.hpp"
#include "ck/tensor_operation/gpu/device/convolution_forward_specialization.hpp"
#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/device_grouped_conv_fwd_xdl_instance.hpp"
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
namespace
ck
{
...
...
@@ -17,94 +9,6 @@ namespace tensor_operation {
namespace
device
{
namespace
instance
{
using
F16
=
ck
::
half_t
;
using
F32
=
float
;
using
Empty_Tuple
=
ck
::
Tuple
<>
;
template
<
ck
::
index_t
...
Is
>
using
S
=
ck
::
Sequence
<
Is
...
>
;
using
GNWC
=
ck
::
tensor_layout
::
convolution
::
GNWC
;
using
GKXC
=
ck
::
tensor_layout
::
convolution
::
GKXC
;
using
GNWK
=
ck
::
tensor_layout
::
convolution
::
GNWK
;
using
PassThrough
=
ck
::
tensor_operation
::
element_wise
::
PassThrough
;
static
constexpr
auto
ConvFwdDefault
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Default
;
static
constexpr
auto
ConvFwd1x1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Pad0
;
static
constexpr
auto
ConvFwd1x1S1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Stride1Pad0
;
static
constexpr
auto
GemmMNKPadding
=
ck
::
tensor_operation
::
device
::
GemmSpecialization
::
MNKPadding
;
// Compilation parameters for in[g, n, wi, c] * wei[g, k, x, c] = out[g, n, wo, k]
using
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instances
=
std
::
tuple
<
// clang-format off
// Default
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
32
,
8
,
8
,
32
,
32
,
2
,
4
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
128
,
32
,
8
,
8
,
32
,
32
,
2
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
64
,
32
,
8
,
8
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
32
,
8
,
8
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
8
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
,
64
,
64
,
32
,
8
,
8
,
32
,
32
,
2
,
2
,
S
<
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16
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1
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16
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
64
,
32
,
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32
,
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2
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S
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1
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32
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
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,
64
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,
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
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,
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,
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,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
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F16
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Empty_Tuple
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PassThrough
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PassThrough
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,
ConvFwdDefault
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
,
64
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32
,
32
,
8
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8
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32
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2
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
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32
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64
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32
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8
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8
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32
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16
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,
// Filter1x1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
8
,
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,
32
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
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,
F32
,
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Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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256
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128
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
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,
F32
,
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,
Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
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,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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128
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
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Empty_Tuple
,
GNWK
,
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,
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Empty_Tuple
,
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PassThrough
,
PassThrough
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,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
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GNWK
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Empty_Tuple
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
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PassThrough
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
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PassThrough
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,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
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,
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,
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,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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,
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,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
32
,
32
,
8
,
8
,
32
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32
,
2
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
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,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
,
64
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32
,
32
,
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8
,
32
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32
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2
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
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32
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32
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32
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,
// Filter1x1Stride1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
F16
,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
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,
8
,
32
,
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4
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
32
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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,
Empty_Tuple
,
F16
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
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,
32
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F16
,
F16
,
F32
,
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Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
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,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
,
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Empty_Tuple
,
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PassThrough
,
PassThrough
,
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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Empty_Tuple
,
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Empty_Tuple
,
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PassThrough
,
PassThrough
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
,
GNWK
,
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,
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Empty_Tuple
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PassThrough
,
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ConvFwd1x1S1P0
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GemmMNKPadding
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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Empty_Tuple
,
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,
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PassThrough
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,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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PassThrough
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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,
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,
32
,
64
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
// clang-format on
>
;
void
add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instances
(
std
::
vector
<
std
::
unique_ptr
<
DeviceGroupedConvFwdMultipleD
<
1
,
GNWC
,
...
...
@@ -120,7 +24,26 @@ void add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f16_instances
{});
device_grouped_conv_fwd_xdl_f16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_f16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_f16_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1S1P0
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instance.cpp
View file @
c7c47fd7
// SPDX-License-Identifier: MIT
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include <cstdlib>
#include "ck/ck.hpp"
#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_fwd_multiple_d_xdl_cshuffle.hpp"
#include "ck/tensor_operation/gpu/device/convolution_forward_specialization.hpp"
#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/device_grouped_conv_fwd_xdl_instance.hpp"
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
namespace
ck
{
...
...
@@ -17,93 +9,6 @@ namespace tensor_operation {
namespace
device
{
namespace
instance
{
using
F32
=
float
;
using
Empty_Tuple
=
ck
::
Tuple
<>
;
template
<
ck
::
index_t
...
Is
>
using
S
=
ck
::
Sequence
<
Is
...
>
;
using
GNWC
=
ck
::
tensor_layout
::
convolution
::
GNWC
;
using
GKXC
=
ck
::
tensor_layout
::
convolution
::
GKXC
;
using
GNWK
=
ck
::
tensor_layout
::
convolution
::
GNWK
;
using
PassThrough
=
ck
::
tensor_operation
::
element_wise
::
PassThrough
;
static
constexpr
auto
ConvFwdDefault
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Default
;
static
constexpr
auto
ConvFwd1x1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Pad0
;
static
constexpr
auto
ConvFwd1x1S1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Stride1Pad0
;
static
constexpr
auto
GemmMNKPadding
=
ck
::
tensor_operation
::
device
::
GemmSpecialization
::
MNKPadding
;
// Compilation parameters for in[g, n, wi, c] * wei[g, k, x, c] = out[g, n, wo, k]
using
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instances
=
std
::
tuple
<
// clang-format off
// Default
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
16
,
4
,
4
,
32
,
32
,
4
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
16
,
4
,
4
,
32
,
32
,
2
,
4
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
4
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
,
64
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
32
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
32
,
128
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
,
64
,
32
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
,
32
,
64
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
,
// Filter1x1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
16
,
4
,
4
,
32
,
32
,
4
,
2
,
S
<
4
,
64
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,
S
<
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,
0
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,
S
<
1
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0
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64
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,
S
<
1
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0
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,
S
<
1
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0
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,
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,
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,
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,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
16
,
4
,
4
,
32
,
32
,
2
,
4
,
S
<
4
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64
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,
S
<
1
,
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1
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64
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,
S
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1
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0
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,
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1
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,
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,
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,
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,
1
,
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,
S
<
1
,
16
,
1
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16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
4
,
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,
S
<
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32
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32
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,
S
<
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,
0
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,
S
<
1
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0
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,
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,
4
,
1
,
1
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,
S
<
1
,
8
,
1
,
16
>
,
4
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
2
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S
<
1
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16
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1
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16
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
64
,
16
,
4
,
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,
32
,
32
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2
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32
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32
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<
1
,
16
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1
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,
4
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
16
,
4
,
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,
32
,
32
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2
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<
1
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8
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1
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16
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,
4
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
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16
,
4
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32
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1
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8
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1
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
64
,
16
,
4
,
4
,
32
,
32
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2
,
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1
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1
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S
<
1
,
16
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1
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16
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,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
16
,
4
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4
,
32
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1
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16
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1
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16
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
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32
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16
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
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,
PassThrough
,
PassThrough
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PassThrough
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
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PassThrough
,
PassThrough
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PassThrough
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ConvFwd1x1P0
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GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
,
32
,
64
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16
,
4
,
4
,
32
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32
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1
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1
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S
<
1
,
8
,
1
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8
>
,
4
>
,
// Filter1x1Stride1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
16
,
4
,
4
,
32
,
32
,
4
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16
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
16
,
4
,
4
,
32
,
32
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2
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,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
4
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
128
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
128
,
64
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
32
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
32
,
128
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
16
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
32
,
16
,
4
,
4
,
32
,
32
,
2
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
F32
,
F32
,
F32
,
F32
,
Empty_Tuple
,
F32
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
32
,
64
,
16
,
4
,
4
,
32
,
32
,
1
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
4
,
4
,
1
,
1
,
1
,
S
<
1
,
8
,
1
,
8
>
,
4
>
// clang-format on
>
;
void
add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instances
(
std
::
vector
<
std
::
unique_ptr
<
DeviceGroupedConvFwdMultipleD
<
1
,
GNWC
,
...
...
@@ -119,7 +24,26 @@ void add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_f32_instances
{});
device_grouped_conv_fwd_xdl_f32_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_f32_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_f32_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1S1P0
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv1d_fwd/device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instance.cpp
View file @
c7c47fd7
// SPDX-License-Identifier: MIT
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include <cstdlib>
#include "ck/ck.hpp"
#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_fwd_multiple_d_xdl_cshuffle.hpp"
#include "ck/tensor_operation/gpu/device/convolution_forward_specialization.hpp"
#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/device_grouped_conv_fwd_xdl_instance.hpp"
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
namespace
ck
{
...
...
@@ -17,90 +9,6 @@ namespace tensor_operation {
namespace
device
{
namespace
instance
{
using
Empty_Tuple
=
ck
::
Tuple
<>
;
template
<
ck
::
index_t
...
Is
>
using
S
=
ck
::
Sequence
<
Is
...
>
;
using
GNWC
=
ck
::
tensor_layout
::
convolution
::
GNWC
;
using
GKXC
=
ck
::
tensor_layout
::
convolution
::
GKXC
;
using
GNWK
=
ck
::
tensor_layout
::
convolution
::
GNWK
;
using
PassThrough
=
ck
::
tensor_operation
::
element_wise
::
PassThrough
;
static
constexpr
auto
ConvFwdDefault
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Default
;
static
constexpr
auto
ConvFwd1x1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Pad0
;
static
constexpr
auto
ConvFwd1x1S1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Stride1Pad0
;
static
constexpr
auto
GemmMNKPadding
=
ck
::
tensor_operation
::
device
::
GemmSpecialization
::
MNKPadding
;
// Compilation parameters for in[g, n, wi, c] * wei[g, k, x, c] = out[g, n, wo, k]
using
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instances
=
std
::
tuple
<
// clang-format off
// Default
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
256
,
32
,
8
,
8
,
32
,
32
,
2
,
4
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
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>
,
S
<
1
,
0
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,
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,
8
,
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,
1
,
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S
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1
,
32
,
1
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8
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
128
,
32
,
8
,
8
,
32
,
32
,
4
,
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,
S
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32
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1
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16
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1
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8
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
128
,
128
,
32
,
8
,
8
,
32
,
32
,
2
,
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,
S
<
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64
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S
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1
,
32
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1
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8
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
128
,
64
,
32
,
8
,
8
,
32
,
32
,
2
,
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,
S
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32
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S
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1
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32
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
32
,
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,
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,
32
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2
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1
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16
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1
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8
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
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,
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,
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,
32
,
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,
32
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2
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16
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,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
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128
,
64
,
32
,
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32
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2
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1
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32
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
32
,
8
,
8
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32
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32
,
1
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32
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
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,
32
,
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,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
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32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
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64
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32
,
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,
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32
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2
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwdDefault
,
GemmMNKPadding
,
1
,
64
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32
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32
,
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32
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1
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16
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1
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,
8
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,
// Filter1x1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
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,
8
,
32
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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128
,
256
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
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,
Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
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,
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,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
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Empty_Tuple
,
GNWK
,
int8_t
,
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,
int32_t
,
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,
Empty_Tuple
,
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,
PassThrough
,
PassThrough
,
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,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
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,
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,
32
,
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,
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,
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
128
,
64
,
128
,
32
,
8
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,
32
,
32
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2
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16
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
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32
,
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32
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2
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
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,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
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,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
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,
Empty_Tuple
,
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,
PassThrough
,
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ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
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Empty_Tuple
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GNWK
,
int8_t
,
int8_t
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int32_t
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Empty_Tuple
,
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,
PassThrough
,
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ConvFwd1x1P0
,
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,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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GKXC
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Empty_Tuple
,
GNWK
,
int8_t
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int32_t
,
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Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
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,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
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GKXC
,
Empty_Tuple
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GNWK
,
int8_t
,
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,
int32_t
,
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,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
,
64
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32
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1P0
,
GemmMNKPadding
,
1
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,
// Filter1x1Stride1Pad0
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| NumGemmK| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MXdl| NXdl| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer|
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Prefetch| Size| Block| Block| Block| | | XDL| XDL| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MXdlPerWave| NXdlPerWave| _MBlock_MWaveMPerXdl| ScalarPerVector|
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | Stage| | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerXdl| _NWaveNPerXdl|
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
256
,
128
,
32
,
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4
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
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GNWK
,
int8_t
,
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Empty_Tuple
,
int8_t
,
PassThrough
,
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,
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
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GNWC
,
GKXC
,
Empty_Tuple
,
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,
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int32_t
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Empty_Tuple
,
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PassThrough
,
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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GNWC
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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,
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ConvFwd1x1S1P0
,
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,
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
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,
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ConvFwd1x1S1P0
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DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
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ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
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S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
256
,
64
,
128
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
64
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
128
,
32
,
32
,
8
,
8
,
32
,
32
,
2
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
32
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
128
,
32
,
128
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
32
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
8
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
64
,
32
,
32
,
8
,
8
,
32
,
32
,
2
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
,
DeviceGroupedConvFwdMultipleD_Xdl_CShuffle
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
int8_t
,
int8_t
,
int32_t
,
int8_t
,
Empty_Tuple
,
int8_t
,
PassThrough
,
PassThrough
,
PassThrough
,
ConvFwd1x1S1P0
,
GemmMNKPadding
,
1
,
64
,
32
,
64
,
32
,
8
,
8
,
32
,
32
,
1
,
2
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
S
<
4
,
16
,
1
>
,
S
<
1
,
0
,
2
>
,
S
<
1
,
0
,
2
>
,
2
,
8
,
8
,
1
,
1
,
1
,
S
<
1
,
16
,
1
,
4
>
,
8
>
// clang-format on
>
;
void
add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instances
(
std
::
vector
<
std
::
unique_ptr
<
DeviceGroupedConvFwdMultipleD
<
1
,
GNWC
,
...
...
@@ -116,7 +24,26 @@ void add_device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv1d_fwd_xdl_gnwc_gkxc_gnwk_int8_instances
{});
device_grouped_conv_fwd_xdl_int8_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_int8_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv_fwd_xdl_int8_instances
<
1
,
GNWC
,
GKXC
,
Empty_Tuple
,
GNWK
,
ConvFwd1x1S1P0
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_common.hpp
deleted
100644 → 0
View file @
f8eb91d7
// SPDX-License-Identifier: MIT
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include <cstdlib>
#include "ck/ck.hpp"
#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
#include "ck/tensor_operation/gpu/device/convolution_forward_specialization.hpp"
#include "ck/tensor_operation/gpu/device/gemm_specialization.hpp"
#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
namespace
ck
{
namespace
tensor_operation
{
namespace
device
{
namespace
instance
{
using
BF16
=
ck
::
bhalf_t
;
using
F16
=
ck
::
half_t
;
using
F32
=
float
;
using
Empty_Tuple
=
ck
::
Tuple
<>
;
template
<
ck
::
index_t
...
Is
>
using
S
=
ck
::
Sequence
<
Is
...
>
;
using
NHWGC
=
ck
::
tensor_layout
::
convolution
::
NHWGC
;
using
GNHWC
=
ck
::
tensor_layout
::
convolution
::
GNHWC
;
using
GKYXC
=
ck
::
tensor_layout
::
convolution
::
GKYXC
;
using
NHWGK
=
ck
::
tensor_layout
::
convolution
::
NHWGK
;
using
GNHWK
=
ck
::
tensor_layout
::
convolution
::
GNHWK
;
using
PassThrough
=
ck
::
tensor_operation
::
element_wise
::
PassThrough
;
static
constexpr
auto
ConvFwdDefault
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Default
;
static
constexpr
auto
ConvFwd1x1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Pad0
;
static
constexpr
auto
ConvFwd1x1S1P0
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
Filter1x1Stride1Pad0
;
static
constexpr
auto
ConvFwdOddC
=
ck
::
tensor_operation
::
device
::
ConvolutionForwardSpecialization
::
OddC
;
static
constexpr
auto
GemmMNKPadding
=
ck
::
tensor_operation
::
device
::
GemmSpecialization
::
MNKPadding
;
}
// namespace instance
}
// namespace device
}
// namespace tensor_operation
}
// namespace ck
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
View file @
c7c47fd7
...
...
@@ -2,7 +2,7 @@
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#include "device_grouped_conv
2d
_fwd_dl_instance.hpp"
#include "
ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/
device_grouped_conv_fwd_dl_instance.hpp"
namespace
ck
{
namespace
tensor_operation
{
...
...
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_dl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
View file @
c7c47fd7
...
...
@@ -2,7 +2,7 @@
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#include "device_grouped_conv
2d
_fwd_dl_instance.hpp"
#include "
ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/
device_grouped_conv_fwd_dl_instance.hpp"
namespace
ck
{
namespace
tensor_operation
{
...
...
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_bf16_instance.cpp
View file @
c7c47fd7
...
...
@@ -2,7 +2,7 @@
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#include "device_grouped_conv
2d
_fwd_xdl_instance.hpp"
#include "
ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/
device_grouped_conv_fwd_xdl_instance.hpp"
namespace
ck
{
namespace
tensor_operation
{
...
...
@@ -24,40 +24,36 @@ void add_device_grouped_conv1d_fwd_xdl_gnhwc_gkyxc_gnhwk_bf16_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_bf16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdDefault
>
{});
device_grouped_conv_fwd_xdl_bf16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_bf16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1P0
>
{});
device_grouped_conv_fwd_xdl_bf16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_bf16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1S1P0
>
{});
device_grouped_conv_fwd_xdl_bf16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1S1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_bf16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdOddC
>
{});
device_grouped_conv_fwd_xdl_bf16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdOddC
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f16_instance.cpp
View file @
c7c47fd7
...
...
@@ -2,7 +2,7 @@
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#include "device_grouped_conv
2d
_fwd_xdl_instance.hpp"
#include "
ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/
device_grouped_conv_fwd_xdl_instance.hpp"
namespace
ck
{
namespace
tensor_operation
{
...
...
@@ -24,40 +24,36 @@ void add_device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f16_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdDefault
>
{});
device_grouped_conv_fwd_xdl_f16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1P0
>
{});
device_grouped_conv_fwd_xdl_f16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1S1P0
>
{});
device_grouped_conv_fwd_xdl_f16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1S1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f16_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdOddC
>
{});
device_grouped_conv_fwd_xdl_f16_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdOddC
>
{});
}
}
// namespace instance
...
...
library/src/tensor_operation_instance/gpu/grouped_conv2d_fwd/device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f32_instance.cpp
View file @
c7c47fd7
...
...
@@ -2,7 +2,7 @@
// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
#include "device_grouped_conv
2d
_fwd_xdl_instance.hpp"
#include "
ck/library/tensor_operation_instance/gpu/grouped_conv_fwd/
device_grouped_conv_fwd_xdl_instance.hpp"
namespace
ck
{
namespace
tensor_operation
{
...
...
@@ -24,40 +24,36 @@ void add_device_grouped_conv2d_fwd_xdl_gnhwc_gkyxc_gnhwk_f32_instances(
PassThrough
>>>&
instances
)
{
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f32_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdDefault
>
{});
device_grouped_conv_fwd_xdl_f32_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdDefault
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f32_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1P0
>
{});
device_grouped_conv_fwd_xdl_f32_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f32_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwd1x1S1P0
>
{});
device_grouped_conv_fwd_xdl_f32_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwd1x1S1P0
>
{});
add_device_operation_instances
(
instances
,
device_grouped_conv2d_fwd_xdl_f32_instances
<
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
Empty_Tuple
,
PassThrough
,
ConvFwdOddC
>
{});
device_grouped_conv_fwd_xdl_f32_instances
<
2
,
GNHWC
,
GKYXC
,
Empty_Tuple
,
GNHWK
,
ConvFwdOddC
>
{});
}
}
// namespace instance
...
...
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