Remove not needed ifdefs

include/ck/tensor_operation/gpu/warp/dpp_gemm.hpp

@@ -450,7 +450,7 @@ struct DppGemm
     {
         static_assert(is_same<BaseType, double>::value || is_same<BaseType, float>::value ||
                           is_same<BaseType, half_t>::value || is_same<BaseType, bhalf_t>::value ||
-                          is_same<BaseType, f8_t>::value || is_same<BaseType, int8_t>::value,
+                          is_same<BaseType, int8_t>::value || is_same<BaseType, f8_t>::value,
                       "base BaseType must be double, float, half, bfloat16, and int8_t!");
 
         static_for<0, KPack / dpp_instr.k_per_dpp, 1>{}([&](auto k) {

include/ck/utility/amd_buffer_addressing.hpp

@@ -415,6 +415,7 @@ __device__ typename vector_type<T, N>::type amd_buffer_load_impl(int32x4_t src_w
             (is_same<T, half_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, bhalf_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, int32_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
+            (is_same<T, f8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, bf8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, int8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)),
         "wrong! not implemented");
@@ -536,12 +537,8 @@ __device__ void amd_buffer_store_impl(const typename vector_type<T, N>::type src
             (is_same<T, half_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, bhalf_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
             (is_same<T, int32_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
-            // #if defined CK_ENABLE_FP8
             (is_same<T, f8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
-            // #endif
-            // #if defined CK_ENABLE_BF8
             (is_same<T, bf8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)) ||
-            // #endif
             (is_same<T, int8_t>::value && (N == 1 || N == 2 || N == 4 || N == 8 || N == 16)),
         "wrong! not implemented");
 

library/include/ck/library/tensor_operation_instance/gpu/grouped_conv_bwd_data/device_grouped_conv_bwd_data_xdl_instance.hpp

@@ -20,6 +20,7 @@ using F16         = ck::half_t;
 using F32  = float;
 using BF8  = ck::bf8_t;
 using F8   = ck::f8_t;
+
 using Empty_Tuple = ck::Tuple<>;
 
 template <ck::index_t... Is>
@@ -145,7 +146,6 @@ using device_grouped_conv_bwd_data_xdl_f32_instances =
         >;
 
 // f16_f16_f16_comp_f8
-// #if defined CK_ENABLE_BF8 && defined CK_ENABLE_FP8
 template <index_t NDimSpatial,
           typename ALayout,
           typename BLayout,
@@ -181,7 +181,7 @@ using device_grouped_conv_bwd_data_xdl_input_fp16_comp_bf8f8_instances =
         DeviceGroupedConvBwdDataMultipleD_Xdl_CShuffle_v1< NDimSpatial, ALayout, BLayout,    DsLayout, ELayout,   F16,   F16,     F32,      F32, Empty_Tuple,   F16,  PassThrough,  PassThrough,    PassThrough,            ConvSpec,  true,  true,             1,    64,    32,    64,    32,   8,   8,   32,   32,       1,       2,       S<4, 16, 1>,     S<1, 0, 2>,     S<1, 0, 2>,              2,              8,              8,         1,        S<4, 8, 1>,     S<0, 2, 1>,     S<0, 2, 1>,              1,              8,              8,         1,            1,            1,     S<1, 16, 1, 4>,                8,  LoopScheduler::Default, BF8, F8>
         // clang-format on
         >;
-// #endif
+
 } // namespace instance
 } // namespace device
 } // namespace tensor_operation

library/src/tensor_operation_instance/gpu/grouped_conv3d_bwd_data/xdl/device_grouped_conv3d_bwd_data_xdl_ndhwgc_gkzyxc_ndhwgk_input_f16_comp_bf8_f8_instance.cpp

@@ -45,6 +45,7 @@ void add_device_grouped_conv3d_bwd_data_xdl_ndhwgk_gkzyxc_ndhwgc_input_f16_comp_
                                        NDHWGC,
                                        ConvBwdDataFilter1x1Stride1Pad0>{});
 }
+
 } // namespace instance
 } // namespace device
 } // namespace tensor_operation

library/src/tensor_operation_instance/gpu/grouped_conv3d_fwd/xdl/device_grouped_conv3d_fwd_xdl_ndhwgc_gkzyxc_ndhwgk_f16_comp_fp8_instance.cpp

@@ -49,6 +49,7 @@ void add_device_grouped_conv3d_fwd_xdl_ndhwgc_gkzyxc_ndhwgk_f16_comp_f8_instance
                                                           NDHWGK,
                                                           ConvFwd1x1S1P0>{});
 }
+
 } // namespace instance
 } // namespace device
 } // namespace tensor_operation