set(INSTANCE_LIBRARY_NAME device_gemm_instance)

add_instance_library(${INSTANCE_LIBRARY_NAME}
  device_gemm_dl_f16_f16_f16_km_kn_mn_instance.cpp
  device_gemm_dl_f16_f16_f16_km_kn_mn_irregular_instance.cpp
  device_gemm_dl_f16_f16_f16_km_nk_mn_instance.cpp
  device_gemm_dl_f16_f16_f16_km_nk_mn_irregular_instance.cpp
  device_gemm_dl_f16_f16_f16_mk_kn_mn_instance.cpp
  device_gemm_dl_f16_f16_f16_mk_kn_mn_irregular_instance.cpp
  device_gemm_dl_f16_f16_f16_mk_nk_mn_instance.cpp
  device_gemm_dl_f16_f16_f16_mk_nk_mn_irregular_instance.cpp
  device_gemm_dl_f32_f32_f32_km_kn_mn_instance.cpp
  device_gemm_dl_f32_f32_f32_km_nk_mn_instance.cpp
  device_gemm_dl_f32_f32_f32_mk_kn_mn_instance.cpp
  device_gemm_dl_f32_f32_f32_mk_nk_mn_instance.cpp
  device_gemm_dl_i8_i8_i8_km_kn_mn_instance.cpp
  device_gemm_dl_i8_i8_i8_km_kn_mn_irregular_instance.cpp
  device_gemm_dl_i8_i8_i8_km_nk_mn_instance.cpp
  device_gemm_dl_i8_i8_i8_km_nk_mn_irregular_instance.cpp
  device_gemm_dl_i8_i8_i8_mk_kn_mn_instance.cpp
  device_gemm_dl_i8_i8_i8_mk_kn_mn_irregular_instance.cpp
  device_gemm_dl_i8_i8_i8_mk_nk_mn_instance.cpp
  device_gemm_dl_i8_i8_i8_mk_nk_mn_irregular_instance.cpp
  device_gemm_xdl_c_shuffle_2_stage_f16_f16_f16_mk_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_bf16_bf16_bf16_km_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_bf16_bf16_bf16_km_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_bf16_bf16_bf16_mk_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_bf16_bf16_bf16_mk_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f16_f16_f16_km_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f16_f16_f16_km_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f16_f16_f16_mk_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f16_f16_f16_mk_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f32_f32_f32_km_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f32_f32_f32_km_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f32_f32_f32_mk_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_f32_f32_f32_mk_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_i8_i8_i8_km_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_i8_i8_i8_km_nk_mn_instance.cpp
  device_gemm_xdl_c_shuffle_i8_i8_i8_mk_kn_mn_instance.cpp
  device_gemm_xdl_c_shuffle_i8_i8_i8_mk_nk_mn_instance.cpp

  device_gemm_xdl_f16_f16_f16/km_kn_mn_add_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v2_opt_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_irregular_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_irregular_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_kn_mn_irregular_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_add_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v2_opt_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_irregular_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_irregular_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/km_nk_mn_irregular_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_add_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_irregular_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_irregular_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_kn_mn_irregular_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_add_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v2_opt_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_interwave_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_irregular_default_pipeline_v1_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_irregular_default_pipeline_v2_instance.cpp
  device_gemm_xdl_f16_f16_f16/mk_nk_mn_irregular_interwave_pipeline_v1_instance.cpp

  device_gemm_xdl_f32_f32_f32_km_kn_mn_instance.cpp
  device_gemm_xdl_f32_f32_f32_km_nk_mn_instance.cpp
  device_gemm_xdl_f32_f32_f32_mk_kn_mn_instance.cpp
  device_gemm_xdl_f32_f32_f32_mk_nk_mn_instance.cpp
  device_gemm_xdl_f64_f64_f64_km_kn_mn_instance.cpp
  device_gemm_xdl_f64_f64_f64_km_nk_mn_instance.cpp
  device_gemm_xdl_f64_f64_f64_mk_kn_mn_instance.cpp
  device_gemm_xdl_f64_f64_f64_mk_nk_mn_instance.cpp 
)

set(ENABLE_PIPELINE_V2_OPT OFF)

if (ENABLE_PIPELINE_V2_OPT)
# layout=NT
set_source_files_properties(device_gemm_xdl_f16_f16_f16/km_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
  COMPILE_OPTIONS ";;"
  COMPILE_DEFINITIONS ";CK_EXPERIMENTAL_PIPELINE_V2_IGLP_OPT=1;CK_USE_WAVES_PER_EU=1;CK_MIN_WAVES_PER_EU=1;CK_MAX_WAVES_PER_EU=1;")
# layout=NN
set_source_files_properties(device_gemm_xdl_f16_f16_f16/km_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
  COMPILE_OPTIONS ";-mllvm;-amdgpu-enable-max-ilp-scheduling-strategy;"
  COMPILE_DEFINITIONS ";CK_EXPERIMENTAL_PIPELINE_V2_IGLP_OPT=1;CK_USE_WAVES_PER_EU=1;CK_MIN_WAVES_PER_EU=1;CK_MAX_WAVES_PER_EU=1;")
# layout=TT
set_source_files_properties(device_gemm_xdl_f16_f16_f16/mk_kn_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
  COMPILE_OPTIONS ";-mllvm;-amdgpu-enable-max-ilp-scheduling-strategy;"
  COMPILE_DEFINITIONS ";CK_USE_WAVES_PER_EU=1;CK_MIN_WAVES_PER_EU=1;CK_MAX_WAVES_PER_EU=1;")
# layout=TN
set_source_files_properties(device_gemm_xdl_f16_f16_f16/mk_nk_mn_default_pipeline_v2_opt_instance.cpp PROPERTIES
  COMPILE_OPTIONS ";-mllvm;-amdgpu-enable-max-ilp-scheduling-strategy;"
  COMPILE_DEFINITIONS ";CK_EXPERIMENTAL_PIPELINE_V2_IGLP_OPT=1;CK_USE_WAVES_PER_EU=1;CK_MIN_WAVES_PER_EU=1;CK_MAX_WAVES_PER_EU=1;")
endif()
