{"exp_name": "CdmTCP-gt-cv-switch-8", "metadata": {}, "start_time": 1607494444.3694484, "end_time": 1607574793.798286, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9411182272", "    m_axis_ctrl_dma_read_desc_ram_addr = 1536", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 12", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516351840", "    m_axis_ctrl_dma_write_desc_ram_addr = 736", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 23", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 7", "    m_axis_data_dma_write_desc_dma_addr = 9277534208", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 29", "    s_axil_rdata = 2147483675", "    m_axil_csr_awaddr = 7340908", "    m_axil_csr_wdata = 2147483675", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7340908", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474724000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9396567232", "    m_axis_ctrl_dma_read_desc_ram_addr = 2688", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 21", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516024832", "    m_axis_ctrl_dma_write_desc_ram_addr = 160", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 5", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 29", "    m_axis_data_dma_write_desc_dma_addr = 8369745920", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 21", "    s_axil_rdata = 2147483666", "    m_axil_csr_awaddr = 7347788", "    m_axil_csr_wdata = 2147483666", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7347788", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474796000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9406777744", "    m_axis_ctrl_dma_read_desc_ram_addr = 2944", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 23", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516086592", "    m_axis_ctrl_dma_write_desc_ram_addr = 448", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 14", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 28", "    m_axis_data_dma_write_desc_dma_addr = 8920858624", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 25", "    s_axil_rdata = 2147483664", "    m_axil_csr_awaddr = 7343628", "    m_axil_csr_wdata = 2147483664", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7343628", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474592000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9399912672", "    m_axis_ctrl_dma_read_desc_ram_addr = 2816", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 22", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515861088", "    m_axis_ctrl_dma_write_desc_ram_addr = 160", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 5", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 15", "    m_axis_data_dma_write_desc_dma_addr = 8962027520", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 15", "    s_axil_rdata = 2147483661", "    m_axil_csr_awaddr = 7344556", "    m_axil_csr_wdata = 2147483661", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7344556", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474676000"], "stderr": []}, "nic.server.4.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.4.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9410053040", "    m_axis_ctrl_dma_read_desc_ram_addr = 896", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 7", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515073600", "    m_axis_ctrl_dma_write_desc_ram_addr = 160", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 5", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 25", "    m_axis_data_dma_write_desc_dma_addr = 9366556672", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 12", "    s_axil_rdata = 2147483652", "    m_axil_csr_awaddr = 7340172", "    m_axil_csr_wdata = 2147483652", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7340172", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474764000"], "stderr": []}, "nic.server.5.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.5.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9397191744", "    m_axis_ctrl_dma_read_desc_ram_addr = 2304", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 18", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516488192", "    m_axis_ctrl_dma_write_desc_ram_addr = 672", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 21", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 24", "    m_axis_data_dma_write_desc_dma_addr = 8099479552", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 19", "    s_axil_rdata = 2147483679", "    m_axil_csr_awaddr = 7348204", "    m_axil_csr_wdata = 2147483679", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7348204", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474672000"], "stderr": []}, "nic.server.6.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.6.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.6.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.6.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9411070176", "    m_axis_ctrl_dma_read_desc_ram_addr = 512", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 4", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516287840", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 21", "    m_axis_data_dma_write_desc_dma_addr = 8372527104", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 20", "    s_axil_rdata = 2147483673", "    m_axil_csr_awaddr = 7340844", "    m_axil_csr_wdata = 2147483673", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7340844", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474860000"], "stderr": []}, "nic.server.7.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.7.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.7.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.7.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9400481904", "    m_axis_ctrl_dma_read_desc_ram_addr = 3840", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 30", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516250368", "    m_axis_ctrl_dma_write_desc_ram_addr = 928", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 29", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 11", "    m_axis_data_dma_write_desc_dma_addr = 8858148864", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 15", "    s_axil_rdata = 2147483671", "    m_axil_csr_awaddr = 7344876", "    m_axil_csr_wdata = 2147483671", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7344876", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474868000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.0.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.0.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9454877504", "    m_axis_ctrl_dma_read_desc_ram_addr = 1664", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 13", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515287360", "    m_axis_ctrl_dma_write_desc_ram_addr = 992", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 31", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 15", "    m_axis_data_dma_write_desc_dma_addr = 9380294656", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 21", "    s_axil_rdata = 2147483658", "    m_axil_csr_awaddr = 4198732", "    m_axil_csr_wdata = 2147483658", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198732", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474780000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.1.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.1.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9462412096", "    m_axis_ctrl_dma_read_desc_ram_addr = 2816", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 22", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515915520", "    m_axis_ctrl_dma_write_desc_ram_addr = 32", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 1", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 8", "    m_axis_data_dma_write_desc_dma_addr = 9154404352", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 6", "    s_axil_rdata = 2147483661", "    m_axil_csr_awaddr = 4197804", "    m_axil_csr_wdata = 2147483661", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4197804", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474424000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.2.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.2.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9429067392", "    m_axis_ctrl_dma_read_desc_ram_addr = 3072", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 24", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516197952", "    m_axis_ctrl_dma_write_desc_ram_addr = 96", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 3", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 13", "    m_axis_data_dma_write_desc_dma_addr = 8600674304", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 4", "    s_axil_rdata = 2147483668", "    m_axil_csr_awaddr = 4201100", "    m_axil_csr_wdata = 2147483668", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4201100", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474560000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.3.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.3.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9468191680", "    m_axis_ctrl_dma_read_desc_ram_addr = 2944", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 23", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515161664", "    m_axis_ctrl_dma_write_desc_ram_addr = 128", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 4", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 13", "    m_axis_data_dma_write_desc_dma_addr = 8853049344", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 13", "    s_axil_rdata = 2147483654", "    m_axil_csr_awaddr = 4197580", "    m_axil_csr_wdata = 2147483654", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4197580", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474772000"], "stderr": []}, "nic.client.4.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.4.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.4.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9484766976", "    m_axis_ctrl_dma_read_desc_ram_addr = 1024", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 8", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516110784", "    m_axis_ctrl_dma_write_desc_ram_addr = 64", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 2", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 6", "    m_axis_data_dma_write_desc_dma_addr = 8940408832", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 1", "    s_axil_rdata = 2147483667", "    m_axil_csr_awaddr = 4195948", "    m_axil_csr_wdata = 2147483667", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4195948", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474640000"], "stderr": []}, "nic.client.5.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.5.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.5.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9484964160", "    m_axis_ctrl_dma_read_desc_ram_addr = 2432", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 19", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516046880", "    m_axis_ctrl_dma_write_desc_ram_addr = 960", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 30", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 1", "    m_axis_data_dma_write_desc_dma_addr = 9321885696", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 5", "    s_axil_rdata = 2147483667", "    m_axil_csr_awaddr = 4195948", "    m_axil_csr_wdata = 2147483667", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4195948", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474816000"], "stderr": []}, "nic.client.6.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.6.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.6.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.6.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9459213248", "    m_axis_ctrl_dma_read_desc_ram_addr = 640", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 5", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516434208", "    m_axis_ctrl_dma_write_desc_ram_addr = 736", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 23", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 9", "    m_axis_data_dma_write_desc_dma_addr = 8755167232", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 22", "    s_axil_rdata = 2147483677", "    m_axil_csr_awaddr = 4198316", "    m_axil_csr_wdata = 2147483677", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198316", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469474572000"], "stderr": []}, "nic.client.7.": {"class": "CorundumVerilatorNIC", "cmd": ["/home/hejingli/endhostsim-code/corundum/corundum_verilator", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.7.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.7.", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.7.", "0", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9460769280", "    m_axis_ctrl_dma_read_desc_ram_addr = 3968", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 31", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515096480", "    m_axis_ctrl_dma_write_desc_ram_addr = 192", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 6", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 17", "    m_axis_data_dma_write_desc_dma_addr = 9024061440", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 21", "    s_axil_rdata = 2147483652", "    m_axil_csr_awaddr = 4198540", "    m_axil_csr_wdata = 2147483652", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198540", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:19469473924000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/home/hejingli/endhostsim-code/net_switch/net_switch", "-m", "0", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.4.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.5.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.6.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.server.7.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.3.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.4.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.5.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.6.", "-s", "/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.eth.client.7."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48738", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1886466029959", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.855920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.857920] mqnic 0000:00:02.0: mqnic probe\r", "[    0.857920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.857920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.857920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.857920] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.857920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.857920] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.857920] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.857920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.857920] mqnic 0000:00:02.0: IF count: 1\r", "[    0.857920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.857920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.857920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.857920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.857920] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.863919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.863919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.863919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.863919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.863919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.863919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.863919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.863919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.863919] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.863919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.863919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.863919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.863919] mqnic 0000:00:02.0: Port count: 1\r", "[    0.863919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.863919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.863919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.863919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.088884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.088884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.088884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.088884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.088884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.088884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.088884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.157874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.1 port 5001 connected with 10.0.0.9 port 53066\r", "[  6] local 10.0.0.1 port 5001 connected with 10.0.0.9 port 53068\r", "[    5.433224] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   685 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1886466019959.  Starting simulation...", "info: Entering event queue @ 1886466029959.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1886466030282.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48739", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 2009315713969", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.880917] mqnic: loading out-of-tree module taints kernel.\r", "[    0.881917] mqnic 0000:00:02.0: mqnic probe\r", "[    0.881917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.881917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.881917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.881917] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.881917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.881917] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.881917] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.881917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.881917] mqnic 0000:00:02.0: IF count: 1\r", "[    0.881917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.881917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.882917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.882917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.882917] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.886916] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.886916] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.886916] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.886916] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.886916] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.886916] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.886916] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.886916] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.886916] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.887916] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.887916] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.887916] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.887916] mqnic 0000:00:02.0: Port count: 1\r", "[    0.887916] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.887916] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.887916] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.887916] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.111882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.111882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.111882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.111882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.111882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.111882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.111882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.183871] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.2 port 5001 connected with 10.0.0.10 port 59548\r", "[  6] local 10.0.0.2 port 5001 connected with 10.0.0.10 port 59546\r", "[    5.299245] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 2009315703969.  Starting simulation...", "info: Entering event queue @ 2009315713969.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 2009315714292.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48740", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1895299235911", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.857920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.858920] mqnic 0000:00:02.0: mqnic probe\r", "[    0.858920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.858920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.859919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.859919] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.859919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.859919] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.859919] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.859919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.859919] mqnic 0000:00:02.0: IF count: 1\r", "[    0.859919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.859919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.859919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.859919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.859919] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.864919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.864919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.864919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.864919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.864919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.864919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.864919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.864919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.864919] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.864919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.864919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.864919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.864919] mqnic 0000:00:02.0: Port count: 1\r", "[    0.864919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.864919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.864919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.864919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.089884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.089884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.089884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.089884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.089884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.089884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.089884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.158874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.3 port 5001 connected with 10.0.0.11 port 47202\r", "[  6] local 10.0.0.3 port 5001 connected with 10.0.0.11 port 47204\r", "[    5.485216] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.0 sec   832 MBytes   695 Mbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   690 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1895299225911.  Starting simulation...", "info: Entering event queue @ 1895299235911.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1895299244226.  Starting simulation...", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48741", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1876753123255", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.852920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.853920] mqnic 0000:00:02.0: mqnic probe\r", "[    0.853920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.853920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.853920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.853920] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.853920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.853920] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.853920] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.853920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.853920] mqnic 0000:00:02.0: IF count: 1\r", "[    0.853920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.853920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.854920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.854920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.854920] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.858919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.858919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.858919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.858919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.858919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.858919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.858919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.858919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.858919] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.859919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.859919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.859919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.859919] mqnic 0000:00:02.0: Port count: 1\r", "[    0.859919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.859919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.859919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.859919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.083885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.083885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.083885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.083885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.083885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.083885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.083885] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.152874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.4 port 5001 connected with 10.0.0.12 port 36768\r", "[  6] local 10.0.0.4 port 5001 connected with 10.0.0.12 port 36770\r", "[    5.373233] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.1 sec   832 MBytes   688 Mbits/sec\r", "[  6]  0.0-10.3 sec   832 MBytes   680 Mbits/sec\r", "[SUM]  0.0-10.3 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1876753113255.  Starting simulation...", "info: Entering event queue @ 1876753123255.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1876753123578.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.4": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.4", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.4", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.4.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.4.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.4.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48743", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.4 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.4 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.4.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.4. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.4. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1918319711059", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.873918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.874918] mqnic 0000:00:02.0: mqnic probe\r", "[    0.874918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.874918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.874918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.874918] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.874918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.874918] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.874918] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.874918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.874918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.874918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.874918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.875918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.875918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.875918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.880917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.880917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.880917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.880917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.880917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.880917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.880917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.880917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.880917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.880917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.881917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.881917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.881917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.881917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.881917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.881917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.881917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.105883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.105883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.105883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.105883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.105883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.105883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.105883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.174872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  6] local 10.0.0.5 port 5001 connected with 10.0.0.13 port 40870\r", "[  5] local 10.0.0.5 port 5001 connected with 10.0.0.13 port 40868\r", "[    5.359236] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   682 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1918319701059.  Starting simulation...", "info: Entering event queue @ 1918319711059.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1918319711382.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.5": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.5", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.5", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.5.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.5.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.5.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48744", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.5 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.5 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.5.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.5. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.5. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1934434221751", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.862919] mqnic: loading out-of-tree module taints kernel.\r", "[    0.863919] mqnic 0000:00:02.0: mqnic probe\r", "[    0.863919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.863919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.864919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.864919] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.864919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.864919] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.864919] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.864919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.864919] mqnic 0000:00:02.0: IF count: 1\r", "[    0.864919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.864919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.864919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.864919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.864919] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.869918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.869918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.869918] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.869918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.869918] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.869918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.869918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.869918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.869918] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.869918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.869918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.869918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.869918] mqnic 0000:00:02.0: Port count: 1\r", "[    0.869918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.869918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.869918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.869918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.093884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.094884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.094884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.094884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.094884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.094884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.094884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.163874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.6 port 5001 connected with 10.0.0.14 port 50710\r", "[  6] local 10.0.0.6 port 5001 connected with 10.0.0.14 port 50712\r", "[    5.356236] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   682 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1934434211751.  Starting simulation...", "info: Entering event queue @ 1934434221751.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1934434222074.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.6": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.6", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.6", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.6.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.6.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.6.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48745", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.6 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.6 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.6.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.6. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.6. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1884328564231", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.854920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.856920] mqnic 0000:00:02.0: mqnic probe\r", "[    0.856920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.856920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.856920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.856920] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.856920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.856920] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.856920] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.856920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.856920] mqnic 0000:00:02.0: IF count: 1\r", "[    0.856920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.856920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.856920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.857920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.857920] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.862919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.862919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.862919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.862919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.862919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.862919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.862919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.862919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.862919] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.862919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.862919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.862919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.862919] mqnic 0000:00:02.0: Port count: 1\r", "[    0.862919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.863919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.863919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.863919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.087885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.087885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.087885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.087885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.087885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.087885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.087885] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.157874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.7 port 5001 connected with 10.0.0.15 port 49460\r", "[  6] local 10.0.0.7 port 5001 connected with 10.0.0.15 port 49462\r", "[    5.416227] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   682 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1884328554231.  Starting simulation...", "info: Entering event queue @ 1884328564231.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1884328564554.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.7": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.7", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.7", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.7.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.7.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.7.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48746", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.server.7 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.server.7 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.server.7.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.server.7. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.server.7. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1901638979488", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.864919] mqnic: loading out-of-tree module taints kernel.\r", "[    0.865919] mqnic 0000:00:02.0: mqnic probe\r", "[    0.865919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.865919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.865919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.865919] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.865919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.865919] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.865919] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.865919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.865919] mqnic 0000:00:02.0: IF count: 1\r", "[    0.865919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.865919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.866918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.866918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.866918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.870918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.870918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.870918] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.870918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.870918] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.870918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.870918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.870918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.871918] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.871918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.871918] mqnic 0000:00:02.0: Port count: 1\r", "[    0.871918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.871918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.871918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.871918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.095884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.095884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.095884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.164873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.8 port 5001 connected with 10.0.0.16 port 57960\r", "[  6] local 10.0.0.8 port 5001 connected with 10.0.0.16 port 57962\r", "[    5.417227] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   681 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1901638969488.  Starting simulation...", "info: Entering event queue @ 1901638979488.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1901638979811.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.0", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.0", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.0.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.0.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48747", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.0 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.0 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.0. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.0. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1927139722885", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.867918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.868918] mqnic 0000:00:02.0: mqnic probe\r", "[    0.868918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.868918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.868918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.868918] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.868918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.868918] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.868918] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.868918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.868918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.868918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.868918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.869918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.869918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.869918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.873917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.873917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.873917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.873917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.873917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.873917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.873917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.874917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.874917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.874917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.874917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.874917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.874917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.874917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.874917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.874917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.874917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.098883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.098883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.098883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.167873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.9/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.9 port 53066 connected with 10.0.0.1 port 5001\r", "[  4] local 10.0.0.9 port 53068 connected with 10.0.0.1 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.444223] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   685 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1927139712885.  Starting simulation...", "info: Entering event queue @ 1927139722885.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1927139723208.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.1", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.1", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.1.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.1.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48748", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.1 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.1 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.1. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.1. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1892996476309", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.860920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.861919] mqnic 0000:00:02.0: mqnic probe\r", "[    0.861919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.861919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.861919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.861919] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.861919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.861919] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.861919] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.861919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.862919] mqnic 0000:00:02.0: IF count: 1\r", "[    0.862919] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.862919] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.862919] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.862919] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.862919] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.866919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.866919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.866919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.866919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.866919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.867918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.867918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.867918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.867918] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.867918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.867918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.867918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.867918] mqnic 0000:00:02.0: Port count: 1\r", "[    0.867918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.867918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.867918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.867918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.091884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.091884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.091884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.091884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.091884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.091884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.091884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.161874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.10/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.10 port 59548 connected with 10.0.0.2 port 5001\r", "[  4] local 10.0.0.10 port 59546 connected with 10.0.0.2 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.361236] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   690 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1892996466309.  Starting simulation...", "info: Entering event queue @ 1892996476309.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1892996476632.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.2", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.2", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.2.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.2.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48749", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.2 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.2 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.2. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.2. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1916452739899", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.866918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.867918] mqnic 0000:00:02.0: mqnic probe\r", "[    0.867918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.867918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.867918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.867918] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.867918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.867918] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.867918] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.867918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.867918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.867918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.867918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.867918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.868918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.868918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.873917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.873917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.873917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.873917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.873917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.873917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.873917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.873917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.873917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.873917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.873917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.874917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.874917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.874917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.874917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.874917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.874917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.098883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.098883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.098883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.098883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.167873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.11/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.11 port 47202 connected with 10.0.0.3 port 5001\r", "[  5] local 10.0.0.11 port 47204 connected with 10.0.0.3 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.528210] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  3.0- 4.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  5.0- 6.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.0 sec   832 MBytes   695 Mbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  9.0-10.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   690 Mbits/sec\r", "[SUM]  0.0-10.1 sec  1.62 GBytes  1.38 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1916452729899.  Starting simulation...", "info: Entering event queue @ 1916452739899.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1916452740222.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.3", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.3", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.3.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.3.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48750", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.3 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.3 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.3. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.3. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1888287054778", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.866920] mqnic: loading out-of-tree module taints kernel.\r", "[    0.867920] mqnic 0000:00:02.0: mqnic probe\r", "[    0.867920] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.867920] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.867920] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.867920] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.867920] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.867920] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.868920] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.868920] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.868920] mqnic 0000:00:02.0: IF count: 1\r", "[    0.868920] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.868920] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.868920] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.868920] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.868920] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.872919] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.872919] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.872919] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.873919] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.873919] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.873919] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.873919] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.873919] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.873919] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.873919] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.873919] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.873919] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.873919] mqnic 0000:00:02.0: Port count: 1\r", "[    0.873919] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.873919] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.873919] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.873919] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.097885] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.097885] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.098885] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.098885] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.098885] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.098885] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.098885] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.167874] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.12/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.12 port 36768 connected with 10.0.0.4 port 5001\r", "[  5] local 10.0.0.12 port 36770 connected with 10.0.0.4 port 5001\r", "[    4.632347] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  0.0-10.3 sec   832 MBytes   681 Mbits/sec\r", "[SUM]  0.0-10.3 sec  1.62 GBytes  1.36 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1888287044778.  Starting simulation...", "info: Entering event queue @ 1888287054778.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1888287055101.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.4": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.4", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.4", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.4.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.4.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.4.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48751", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.4 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.4 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.4.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.4. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.4. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1886411442601", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.862918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.864918] mqnic 0000:00:02.0: mqnic probe\r", "[    0.864918] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.864918] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.864918] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.864918] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.864918] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.864918] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.864918] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.864918] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.864918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.864918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.864918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.864918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.865918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.865918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.870917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.870917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.870917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.870917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.870917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.870917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.870917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.870917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.870917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.870917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.870917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.870917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.871917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.871917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.871917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.871917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.871917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.095883] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.095883] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.095883] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.095883] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.095883] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.095883] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.095883] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.164873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.13/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.5 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.5, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.13 port 40870 connected with 10.0.0.5 port 5001\r", "[  4] local 10.0.0.13 port 40868 connected with 10.0.0.5 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.329240] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   682 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1886411432601.  Starting simulation...", "info: Entering event queue @ 1886411442601.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1886411442924.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.5": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.5", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.5", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.5.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.5.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.5.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48752", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.5 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.5 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.5.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.5. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.5. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1910198449783", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.864919] mqnic: loading out-of-tree module taints kernel.\r", "[    0.865919] mqnic 0000:00:02.0: mqnic probe\r", "[    0.865919] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.865919] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.865919] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.865919] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.865919] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.865919] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.865919] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.865919] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.866918] mqnic 0000:00:02.0: IF count: 1\r", "[    0.866918] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.866918] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.866918] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.866918] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.866918] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.870918] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.870918] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.870918] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.870918] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.870918] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.871918] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.871918] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.871918] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.871918] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.871918] mqnic 0000:00:02.0: Port count: 1\r", "[    0.871918] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.871918] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.871918] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.871918] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.095884] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.095884] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.095884] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.095884] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.096884] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.165873] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.14/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.6 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.6, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.14 port 50710 connected with 10.0.0.6 port 5001\r", "[  5] local 10.0.0.14 port 50712 connected with 10.0.0.6 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.344238] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1910198439783.  Starting simulation...", "info: Entering event queue @ 1910198449783.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1910198450106.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.6": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.6", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.6", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.6.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.6.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.6.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48753", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.6 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.6 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.6.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.6. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.6. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1968977995732", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.868918] mqnic: loading out-of-tree module taints kernel.\r", "[    0.869917] mqnic 0000:00:02.0: mqnic probe\r", "[    0.869917] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.869917] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.869917] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.869917] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.869917] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.870917] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.870917] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.870917] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.870917] mqnic 0000:00:02.0: IF count: 1\r", "[    0.870917] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.870917] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.870917] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.870917] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.870917] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.874917] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.874917] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.875917] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.875917] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.875917] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.875917] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.875917] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.875917] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.875917] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.875917] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.875917] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.875917] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.875917] mqnic 0000:00:02.0: Port count: 1\r", "[    0.875917] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.875917] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.875917] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.875917] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.099882] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.099882] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.099882] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.099882] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.100882] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.100882] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.100882] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.169872] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.15/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.7 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.7, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.15 port 49460 connected with 10.0.0.7 port 5001\r", "[  5] local 10.0.0.15 port 49462 connected with 10.0.0.7 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.292245] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep infinity\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1968977985732.  Starting simulation...", "info: Entering event queue @ 1968977995732.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1968978004047.  Starting simulation...", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.7": {"class": "Gem5Host", "cmd": ["/home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt", "--outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.7", "/home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.7", "--kernel=/home/hejingli/endhostsim-code/images/vmlinux", "--disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.7.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.7.", "--cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.7.", "--cosim-sync", "--cosim-sync_mode=0", "--cosim-pci-lat=500", "--cosim-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled Dec  3 2020 17:56:02", "gem5 started Dec  9 2020 07:14:05", "gem5 executing on spyder09, pid 48754", "command line: /home/hejingli/endhostsim-code/gem5/build/X86/gem5.opt --outdir=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/gem5-out.client.7 /home/hejingli/endhostsim-code/gem5/configs/cosim/cosim.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/home/hejingli/endhostsim-code/experiments/out/CdmTCP-gt-cv-switch-8/0/gem5-cp.client.7 --kernel=/home/hejingli/endhostsim-code/images/vmlinux --disk-image=/home/hejingli/endhostsim-code/images/output-base/base.raw --disk-image=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/cfg.client.7.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --cosim-pci=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.pci.client.7. --cosim-shm=/local/var/tmp/hejingli/CdmTCP-gt-cv-switch-8/1/nic.shm.client.7. --cosim-sync --cosim-sync_mode=0 --cosim-pci-lat=500 --cosim-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "      0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 00:00:00 2012", "Switch at curTick count:10000", "Switched CPUS @ tick 1953548024149", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.880916] mqnic: loading out-of-tree module taints kernel.\r", "[    0.882916] mqnic 0000:00:02.0: mqnic probe\r", "[    0.882916] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.882916] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.882916] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.882916] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.882916] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.882916] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.882916] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.882916] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.882916] mqnic 0000:00:02.0: IF count: 1\r", "[    0.882916] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.882916] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.882916] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.882916] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.882916] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.888915] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.888915] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.888915] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.888915] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.888915] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.888915] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.888915] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.888915] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.888915] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.888915] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.888915] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.888915] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.888915] mqnic 0000:00:02.0: Port count: 1\r", "[    0.888915] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.888915] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.888915] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.888915] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    1.113880] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    1.113880] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    1.113880] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    1.113880] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    1.113880] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    1.113880] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    1.113880] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.182870] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.16/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.8 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.8, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.16 port 57960 connected with 10.0.0.8 port 5001\r", "[  5] local 10.0.0.16 port 57962 connected with 10.0.0.8 port 5001\r", "[    5.260250] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   683 Mbits/sec\r", "[  5]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   681 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r", "+ sleep 4\r", "+ m5 exit\r", "Exiting @ tick 19469473889481 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /home/hejingli/endhostsim-code/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1953548014149.  Starting simulation...", "info: Entering event queue @ 1953548024149.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1953548024472.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}