{"exp_name": "mode-1-gt-cv-switch-4", "metadata": {}, "start_time": 1620303610.263131, "end_time": 1620323891.1757264, "sims": {"nic.server.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.0.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.0.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9411012368", "    m_axis_ctrl_dma_read_desc_ram_addr = 2816", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 22", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516521312", "    m_axis_ctrl_dma_write_desc_ram_addr = 352", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 11", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 13", "    m_axis_data_dma_write_desc_dma_addr = 9293697024", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 6", "    s_axil_rdata = 2147483670", "    m_axil_csr_awaddr = 7340748", "    m_axil_csr_wdata = 2147483670", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7340748", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.server.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.1.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.1.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.1.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9401612224", "    m_axis_ctrl_dma_read_desc_ram_addr = 2688", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 21", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516184320", "    m_axis_ctrl_dma_write_desc_ram_addr = 288", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 9", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 23", "    m_axis_data_dma_write_desc_dma_addr = 8653058048", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 27", "    s_axil_rdata = 2147483662", "    m_axil_csr_awaddr = 7345612", "    m_axil_csr_wdata = 2147483662", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7345612", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.server.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.2.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.2.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.2.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9400519760", "    m_axis_ctrl_dma_read_desc_ram_addr = 2560", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 20", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516319584", "    m_axis_ctrl_dma_write_desc_ram_addr = 832", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 26", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 22", "    m_axis_data_dma_write_desc_dma_addr = 8769257472", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 21", "    s_axil_rdata = 2147483667", "    m_axil_csr_awaddr = 7344748", "    m_axil_csr_wdata = 2147483667", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7344748", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.server.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.3.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.3.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.3.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9396501520", "    m_axis_ctrl_dma_read_desc_ram_addr = 2560", "    m_axis_ctrl_dma_read_desc_len = 16", "    m_axis_ctrl_dma_read_desc_tag = 20", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516286848", "    m_axis_ctrl_dma_write_desc_ram_addr = 64", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 2", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 19", "    m_axis_data_dma_write_desc_dma_addr = 8907472896", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 17", "    s_axil_rdata = 2147483662", "    m_axil_csr_awaddr = 7347660", "    m_axil_csr_wdata = 2147483662", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 7347660", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.client.0.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.0.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.0.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.0.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9456426112", "    m_axis_ctrl_dma_read_desc_ram_addr = 2944", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 23", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516206816", "    m_axis_ctrl_dma_write_desc_ram_addr = 576", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 18", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 5", "    m_axis_data_dma_write_desc_dma_addr = 8689205248", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 18", "    s_axil_rdata = 2147483662", "    m_axil_csr_awaddr = 4198860", "    m_axil_csr_wdata = 2147483662", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198860", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.client.1.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.1.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.1.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.1.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9497009984", "    m_axis_ctrl_dma_read_desc_ram_addr = 2816", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 22", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516073856", "    m_axis_ctrl_dma_write_desc_ram_addr = 864", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 27", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 16", "    m_axis_data_dma_write_desc_dma_addr = 8354144256", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 28", "    s_axil_rdata = 2147483657", "    m_axil_csr_awaddr = 4194604", "    m_axil_csr_wdata = 2147483657", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4194604", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.client.2.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.2.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.2.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.2.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9461838208", "    m_axis_ctrl_dma_read_desc_ram_addr = 2688", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 21", "    m_axis_ctrl_dma_write_desc_dma_addr = 9515968192", "    m_axis_ctrl_dma_write_desc_ram_addr = 640", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 20", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 30", "    m_axis_data_dma_write_desc_dma_addr = 9137975296", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 1", "    s_axil_rdata = 2147483652", "    m_axil_csr_awaddr = 4198540", "    m_axil_csr_wdata = 2147483652", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4198540", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311777504000"], "stderr": []}, "nic.client.3.": {"class": "CorundumVerilatorNIC", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/nic//corundum/corundum_verilator", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.3.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.3.", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.3.", "1", "0", "500", "500", "500", "250"], "stdout": ["eth connection accepted", "eth intro sent", "pci connection accepted", "pci intro sent", "pci host info received", "eth net info received", "sync_pci=1  sync_eth=1", "Addressing configuration for axil_interconnect instance TOP.interface.axil_interconnect_inst", " 0 ( 0): 000000 / 19 -- 000000-07ffff", " 1 ( 0): 080000 / 19 -- 080000-0fffff", " 2 ( 0): 100000 / 20 -- 100000-1fffff", " 3 ( 0): 200000 / 21 -- 200000-3fffff", " 4 ( 0): 400000 / 21 -- 400000-5fffff", " 5 ( 0): 600000 / 20 -- 600000-6fffff", " 6 ( 0): 700000 / 20 -- 700000-7fffff", " 7 ( 0): 800000 / 21 -- 800000-9fffff", "Addressing configuration for axil_interconnect instance TOP.interface.port[0].port_inst.axil_interconnect_inst", " 0 ( 0): 000000 / 20 -- 000000-0fffff", " 1 ( 0): 100000 / 20 -- 100000-1fffff", "    m_axis_ctrl_dma_read_desc_dma_addr = 9422041216", "    m_axis_ctrl_dma_read_desc_ram_addr = 2688", "    m_axis_ctrl_dma_read_desc_len = 64", "    m_axis_ctrl_dma_read_desc_tag = 21", "    m_axis_ctrl_dma_write_desc_dma_addr = 9516302752", "    m_axis_ctrl_dma_write_desc_ram_addr = 256", "    m_axis_ctrl_dma_write_desc_len = 32", "    m_axis_ctrl_dma_write_desc_tag = 8", "    m_axis_data_dma_read_desc_ram_addr = 66", "    m_axis_data_dma_read_desc_tag = 27", "    m_axis_data_dma_write_desc_dma_addr = 9329471488", "    m_axis_data_dma_write_desc_len = 66", "    m_axis_data_dma_write_desc_tag = 5", "    s_axil_rdata = 2147483665", "    m_axil_csr_awaddr = 4202028", "    m_axil_csr_wdata = 2147483665", "    m_axil_csr_wstrb = 15", "    m_axil_csr_araddr = 4202028", "    ctrl_dma_ram_wr_cmd_ready = 255", "    ctrl_dma_ram_rd_cmd_ready = 255", "    data_dma_ram_wr_cmd_ready = 255", "    data_dma_ram_rd_cmd_ready = 255", "    tx_axis_tkeep = 3", "    tx_axis_tlast = 1", "    rx_axis_tready = 1", "", "", "main_time:15311776928000"], "stderr": []}, "net.": {"class": "SwitchNet", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/net/switch/net_switch", "-m", "1", "-S", "500", "-E", "500", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.0.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.1.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.2.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.server.3.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.0.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.1.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.2.", "-s", "/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.eth.client.3."], "stdout": ["start polling"], "stderr": []}, "host.server.0": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.0", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.0", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.0.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.0.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21271", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.0 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.0 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.0. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.0. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1309607276815", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.753932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.754932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.754932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.755931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.755931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.755931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.755931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.755931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.755931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.755931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.755931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.755931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.755931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.755931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.755931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.755931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.760931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.760931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.760931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.760931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.760931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.760931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.760931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.760931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.760931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.760931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.760931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.760931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.760931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.984897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.985896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.985896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.055886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.1/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 35154\r", "[  6] local 10.0.0.1 port 5001 connected with 10.0.0.5 port 35156\r", "[    5.332236] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  5]  0.0-10.3 sec   864 MBytes   706 Mbits/sec\r", "[SUM]  0.0-10.3 sec  1.66 GBytes  1.39 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1309607266815.  Starting simulation...", "info: Entering event queue @ 1309607276815.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1309607277138.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.1": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.1", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.1", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.1.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.1.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21272", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.1 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.1 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.1. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.1. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1320297958432", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.756932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.757932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.758932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.758932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.758932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.758932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.758932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.758932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.758932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.758932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.758932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.758932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.758932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.758932] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.758932] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.758932] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.763931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.763931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.763931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.763931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.763931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.763931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.763931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.763931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.763931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.763931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.763931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.763931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.763931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.763931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.763931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.763931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.763931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.988897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.988897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.988897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.988897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.988897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.988897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.988897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.058886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.2/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 37626\r", "[  6] local 10.0.0.2 port 5001 connected with 10.0.0.6 port 37628\r", "[    5.266247] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   684 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1320297948432.  Starting simulation...", "info: Entering event queue @ 1320297958432.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1320297958755.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.2": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.2", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.2", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.2.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.2.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21273", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.2 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.2 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.2. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.2. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1310959526545", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.756931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.757931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.757931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.757931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.757931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.757931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.757931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.757931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.757931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.757931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.758930] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.758930] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.758930] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.762930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.762930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.762930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.762930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.762930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.762930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.762930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.762930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.763930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.763930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.763930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.763930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.763930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.763930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.763930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.987896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.987896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.987896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.987896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.987896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.987896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.987896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.058885] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.3/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  6] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 59266\r", "[  5] local 10.0.0.3 port 5001 connected with 10.0.0.7 port 59264\r", "[    5.283243] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  6]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1310959516545.  Starting simulation...", "info: Entering event queue @ 1310959526545.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1310959526868.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.server.3": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.3", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.3", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.3.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.3.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21274", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.server.3 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.server.3 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.server.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.server.3. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.server.3. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1301299274800", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.754932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.755932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.756932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.756932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.756932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.756932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.756932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.756932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.756932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.756932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.756932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.756932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.756932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.756932] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.756932] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.756932] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.761931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.761931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.761931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.761931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.761931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.761931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.761931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.761931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.761931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.761931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.761931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.761931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.761931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.985897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.986897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.986897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.056886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.4/24 dev eth0\r", "+ iperf -s -l 32M -w 32M\r", "------------------------------------------------------------\r", "Server listening on TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  6] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 60732\r", "[  5] local 10.0.0.4 port 5001 connected with 10.0.0.8 port 60730\r", "[    5.283244] random: crng init done\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  6]  0.0-10.1 sec   800 MBytes   667 Mbits/sec\r", "[  5]  0.0-10.2 sec   864 MBytes   708 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.36 Gbits/sec\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1301299264800.  Starting simulation...", "info: Entering event queue @ 1301299274800.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1301299275123.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.0": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.0", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.0", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.0.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.0.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.0.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21275", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.0 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.0 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.0.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.0. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.0. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1301153022865", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.756931] mqnic: loading out-of-tree module taints kernel.\r", "[    0.757931] mqnic 0000:00:02.0: mqnic probe\r", "[    0.757931] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.757931] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.757931] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.757931] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.757931] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.757931] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.757931] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.757931] mqnic 0000:00:02.0: IF count: 1\r", "[    0.757931] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.757931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.758931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.758931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.763930] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.763930] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.763930] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.763930] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.763930] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.763930] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.763930] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.763930] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.764930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.764930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.764930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.764930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.764930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.764930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.764930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.988896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.988896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.988896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.988896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.059885] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.5/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.1 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.1, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.5 port 35154 connected with 10.0.0.1 port 5001\r", "[  5] local 10.0.0.5 port 35156 connected with 10.0.0.1 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.399226] random: crng init done\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  3.0- 4.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  5.0- 6.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.1 sec   832 MBytes   689 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.3 sec   864 MBytes   706 Mbits/sec\r", "[SUM]  0.0-10.3 sec  1.66 GBytes  1.39 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1301153012865.  Starting simulation...", "info: Entering event queue @ 1301153022865.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1301153023188.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.1": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.1", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.1", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.1.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.1.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.1.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21276", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.1 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.1 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.1.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.1. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.1. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1294357372984", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.743933] mqnic: loading out-of-tree module taints kernel.\r", "[    0.744933] mqnic 0000:00:02.0: mqnic probe\r", "[    0.744933] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.744933] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.744933] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.744933] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.744933] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.744933] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.744933] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.744933] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.744933] mqnic 0000:00:02.0: IF count: 1\r", "[    0.744933] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.744933] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.745933] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.745933] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.745933] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.749932] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.749932] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.749932] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.749932] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.749932] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.749932] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.749932] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.749932] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.749932] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.749932] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.750932] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.750932] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.750932] mqnic 0000:00:02.0: Port count: 1\r", "[    0.750932] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.750932] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.750932] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.750932] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.974898] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.974898] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.974898] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.974898] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.974898] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.974898] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.974898] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.045887] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.6/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.2 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.2, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  4] local 10.0.0.6 port 37626 connected with 10.0.0.2 port 5001\r", "[  5] local 10.0.0.6 port 37628 connected with 10.0.0.2 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.212254] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   684 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1294357362984.  Starting simulation...", "info: Entering event queue @ 1294357372984.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1294357373307.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.2": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.2", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.2", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.2.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.2.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.2.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21277", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.2 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.2 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.2.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.2. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.2. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1294949173591", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.753932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.754932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.754932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.754932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.754932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.754932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.754932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.754932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.754932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.754932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.754932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.754932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.754932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.755931] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.755931] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.755931] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.760931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.760931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.760931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.760931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.760931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.760931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.760931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.760931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.761930] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.761930] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.761930] mqnic 0000:00:02.0: Port count: 1\r", "[    0.761930] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.761930] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.761930] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.761930] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.985896] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.985896] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.985896] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.985896] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.056886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.7/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.3 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.3, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.7 port 59266 connected with 10.0.0.3 port 5001\r", "[  4] local 10.0.0.7 port 59264 connected with 10.0.0.3 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[    5.194257] random: crng init done\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  6.0- 7.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  0.0-10.2 sec   832 MBytes   687 Mbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  9.0-10.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  5]  0.0-10.2 sec   832 MBytes   686 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep 10\r"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1294949163591.  Starting simulation...", "info: Entering event queue @ 1294949173591.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1294949173914.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}, "host.client.3": {"class": "Gem5Host", "cmd": ["/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast", "--outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.3", "/DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py", "--caches", "--l2cache", "--l3cache", "--l1d_size=32kB", "--l1i_size=32kB", "--l2_size=2MB", "--l3_size=32MB", "--l1d_assoc=8", "--l1i_assoc=8", "--l2_assoc=4", "--l3_assoc=16", "--cacheline_size=64", "--cpu-clock=3GHz", "--sys-clock=1GHz", "--checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.3", "--kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "--disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw", "--disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.3.tar", "--cpu-type=TimingSimpleCPU", "--mem-size=8192MB", "--num-cpus=1", "--ddio-enabled", "--ddio-way-part=8", "--mem-type=DDR4_2400_16x4", "-r", "0", "--simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.3.", "--simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.3.", "--simbricks-sync", "--simbricks-sync_mode=1", "--simbricks-pci-lat=500", "--simbricks-sync-int=500"], "stdout": ["gem5 Simulator System.  http://gem5.org", "gem5 is copyrighted software; use the --copyright option for details.", "", "gem5 version 20.0.0.1", "gem5 compiled May  3 2021 11:39:19", "gem5 started May  6 2021 14:20:11", "gem5 executing on spyder09, pid 21278", "command line: /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/build/X86/gem5.fast --outdir=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/gem5-out.client.3 /DS/endhost-networking/work/sim/hejing/simbricks/sims/external/gem5/configs/simbricks/simbricks.py --caches --l2cache --l3cache --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l3_size=32MB --l1d_assoc=8 --l1i_assoc=8 --l2_assoc=4 --l3_assoc=16 --cacheline_size=64 --cpu-clock=3GHz --sys-clock=1GHz --checkpoint-dir=/DS/endhost-networking/work/sim/hejing/simbricks/experiments/out/mode-1-gt-cv-switch-4/0/gem5-cp.client.3 --kernel=/DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux --disk-image=/DS/endhost-networking/work/sim/hejing/simbricks/images/output-base/base.raw --disk-image=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/cfg.client.3.tar --cpu-type=TimingSimpleCPU --mem-size=8192MB --num-cpus=1 --ddio-enabled --ddio-way-part=8 --mem-type=DDR4_2400_16x4 -r 0 --simbricks-pci=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.pci.client.3. --simbricks-shm=/local/var/tmp/hejing-work/mode-1-gt-cv-switch-4/1/nic.shm.client.3. --simbricks-sync --simbricks-sync_mode=1 --simbricks-pci-lat=500 --simbricks-sync-int=500", "", "info: Standard input is not a terminal, disabling listeners.", "CEHCKPOINT RESTORE THINGIE", "Global frequency set at 1000000000000 ticks per second", "Switch at curTick count:10000", "Switched CPUS @ tick 1301937138298", "switching cpus", "**** REAL SIMULATION ****", "+ insmod /tmp/guest/mqnic.ko\r", "[    0.753932] mqnic: loading out-of-tree module taints kernel.\r", "[    0.755932] mqnic 0000:00:02.0: mqnic probe\r", "[    0.755932] mqnic 0000:00:02.0: enabling device (0000 -> 0002)\r", "[    0.755932] mqnic 0000:00:02.0: PCI->APIC IRQ transform: INT A -> IRQ 17\r", "[    0.755932] mqnic 0000:00:02.0: FW ID: 0x00000020\r", "[    0.755932] mqnic 0000:00:02.0: FW version: 0.1\r", "[    0.755932] mqnic 0000:00:02.0: Board ID: 0x43215678\r", "[    0.755932] mqnic 0000:00:02.0: Board version: 0.1\r", "[    0.755932] mqnic 0000:00:02.0: PHC count: 1\r", "[    0.755932] mqnic 0000:00:02.0: PHC offset: 0x00000200\r", "[    0.755932] mqnic 0000:00:02.0: IF count: 1\r", "[    0.755932] mqnic 0000:00:02.0: IF stride: 0x00080000\r", "[    0.755932] mqnic 0000:00:02.0: IF CSR offset: 0x00080000\r", "[    0.755932] mqnic 0000:00:02.0: Failed to read MAC from EEPROM; no EEPROM I2C client registered\r", "[    0.755932] mqnic 0000:00:02.0: registered PHC (index 0)\r", "[    0.756932] mqnic 0000:00:02.0: Creating interface 0\r", "[    0.761931] mqnic 0000:00:02.0: IF ID: 0x00000000\r", "[    0.761931] mqnic 0000:00:02.0: IF features: 0x00000701\r", "[    0.761931] mqnic 0000:00:02.0: Event queue count: 32\r", "[    0.761931] mqnic 0000:00:02.0: Event queue offset: 0x00100000\r", "[    0.761931] mqnic 0000:00:02.0: TX queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: TX queue offset: 0x00200000\r", "[    0.761931] mqnic 0000:00:02.0: TX completion queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: TX completion queue offset: 0x00400000\r", "[    0.761931] mqnic 0000:00:02.0: RX queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: RX queue offset: 0x00600000\r", "[    0.761931] mqnic 0000:00:02.0: RX completion queue count: 256\r", "[    0.761931] mqnic 0000:00:02.0: RX completion queue offset: 0x00700000\r", "[    0.761931] mqnic 0000:00:02.0: Port count: 1\r", "[    0.761931] mqnic 0000:00:02.0: Port offset: 0x00800000\r", "[    0.761931] mqnic 0000:00:02.0: Port stride: 0x00200000\r", "[    0.761931] mqnic 0000:00:02.0: Bad MAC in EEPROM; using random MAC\r", "[    0.762931] mqnic 0000:00:02.0: Max desc block size: 8\r", "[    0.986897] mqnic 0000:00:02.0: Port ID: 0x00000000\r", "[    0.986897] mqnic 0000:00:02.0: Port features: 0x00000701\r", "[    0.986897] mqnic 0000:00:02.0: Port MTU: 2048\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler count: 1\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler offset: 0x00100000\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler stride: 0x00100000\r", "[    0.986897] mqnic 0000:00:02.0: Scheduler type: 0x00000000\r", "+ ip link set dev eth0 up\r", "[    1.056886] mqnic 0000:00:02.0: mqnic_open on port 0\r", "+ ip addr add 10.0.0.8/24 dev eth0\r", "+ sleep 1\r", "+ iperf -l 32M -w 32M -c 10.0.0.4 -i 1 -P 2\r", "------------------------------------------------------------\r", "Client connecting to 10.0.0.4, TCP port 5001\r", "TCP window size:  416 KByte (WARNING: requested 32.0 MByte)\r", "------------------------------------------------------------\r", "[  5] local 10.0.0.8 port 60732 connected with 10.0.0.4 port 5001\r", "[  4] local 10.0.0.8 port 60730 connected with 10.0.0.4 port 5001\r", "[ ID] Interval       Transfer     Bandwidth\r", "[  5]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  0.0- 1.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  0.0- 1.0 sec   192 MBytes  1.61 Gbits/sec\r", "[    5.219253] random: crng init done\r", "[  5]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  4]  1.0- 2.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  1.0- 2.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  2.0- 3.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  2.0- 3.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  3.0- 4.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  3.0- 4.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  4]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  4.0- 5.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  4.0- 5.0 sec   128 MBytes  1.07 Gbits/sec\r", "[  4]  5.0- 6.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  5.0- 6.0 sec  64.0 MBytes   537 Mbits/sec\r", "[SUM]  5.0- 6.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[  5]  6.0- 7.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  6.0- 7.0 sec   192 MBytes  1.61 Gbits/sec\r", "[  5]  7.0- 8.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  4]  7.0- 8.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  7.0- 8.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  8.0- 9.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  8.0- 9.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  8.0- 9.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  5]  9.0-10.0 sec  64.0 MBytes   537 Mbits/sec\r", "[  5]  0.0-10.0 sec   800 MBytes   668 Mbits/sec\r", "[  4]  9.0-10.0 sec  96.0 MBytes   805 Mbits/sec\r", "[SUM]  9.0-10.0 sec   160 MBytes  1.34 Gbits/sec\r", "[  4]  0.0-10.2 sec   864 MBytes   709 Mbits/sec\r", "[SUM]  0.0-10.2 sec  1.62 GBytes  1.37 Gbits/sec\r", "+ sleep 0.5\r", "+ m5 exit\r", "Exiting @ tick 15311776887342 because m5_exit instruction encountered"], "stderr": ["warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer.", "warn: Physical memory size specified is 8192MB which is greater than 3GB.  Twice the number of memory controllers would be created.", "warn: No dot file generated. Please install pydot to generate the dot file and pdf.", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (4096 Mbytes)", "warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (8192 Mbytes)", "info: kernel located at: /DS/endhost-networking/work/sim/hejing/simbricks/images/vmlinux", "warn: Sockets disabled, not accepting terminal connections", "warn: pollInterval=100000000  pciAsync=500000", "warn: Sockets disabled, not accepting gdb connections", "warn: Reading current count from inactive timer.", "warn: TimingPioPort::getAddrRanges()", "warn: TimingPioPort::getAddrRanges()", "info: Entering event queue @ 1301937128298.  Starting simulation...", "info: Entering event queue @ 1301937138298.  Starting simulation...", "warn: PowerState: Already in the requested power state, request ignored", "info: Entering event queue @ 1301937138621.  Starting simulation...", "warn: instruction 'fwait' unimplemented", "warn: instruction 'verw_Mw_or_Rv' unimplemented", "warn: Don't know what interrupt to clear for console.", "warn: Tried to clear PCI interrupt 14"]}}, "success": true}